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PDF W83977TF-A Data sheet ( Hoja de datos )
| Número de pieza | W83977TF-A | |
| Descripción | I/O chip disk drive adapter | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W83877TF
WINBOND I/O
1 page  
TABLE 3-2 WORD LENGTH DEFINITION
DLS1
DLS0
DATA LENGTH
00
5 bits
01
6 bits
10
7 bits
11
8 bits
W83877TF
3.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
7654 321 0
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic
1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO.
In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left
in the FIFO.
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
than these two cases, this bit will be reset to a logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be
set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU
to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO
is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full
word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the
same condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit
to a logical 0.
- 42 -
Publication Release Date: March 1998
Version 0.61
5 Page 
W83877TF
3.2.9 User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
TABLE 3-5 BAUD RATE TABLE
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
Desired Baud Rate
Decimal divisor used to
generate 16X clock
Percent error difference between
desired and actual
50 2304
**
75 1536
**
110 1047
0.18%
134.5
857
0.099%
150 768
**
300 384
**
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
192
96
64
58
48
32
24
16
12
6
**
**
**
0.53%
**
**
**
**
**
**
38400
3
**
57600
2
**
115200
230400
460800
921600
1.5M
1
4 Note 1
2 Note 1
1 Note 1
1 Note 2
**
**
**
**
0%
Note 1: Only use in high speed mode, when FASTA/FASTB bits are set (refer to CR19 bit1 and CR19 bit0).
Note 2: Only use in high speed mode, when TURA/TURB bits are set (refer to CR0C bit7 and bit6).
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
- 48 -
Publication Release Date: March 1998
Version 0.61
11 Page | ||
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