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W83977TF Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83977TF
Beschreibung WINBOND I/O
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W83977TF Datasheet, Funktion
W83877TF
WINBOND I/O






W83977TF Datasheet, Funktion
W83877TF
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In
16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU
reads USR, it will clear this bit to a logical 0.
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in
the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
3.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls the pins of the UART used for handshaking peripherals such as modem, and
controls the diagnostic mode of the UART.
7 6 5 4 32
00 0
10
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as
follows:
(1) SOUT is forced to a logical 1, and SIN is isolated from the communication link instead of
the TSR.
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
(bit 0 of HCR) DSR, RTS ( bit 1 of HCR) CTS, Loopback RI input ( bit 2 of HCR)
RI and IRQ enable ( bit 3 of HCR) DCD .
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
- 43 -
Publication Release Date: March 1998
Version 0.61

6 Page









W83977TF pdf, datenblatt
W83877TF
FEATURES
General:
Plug & Play 1.0A Compliant
Support 8 IRQs (ISA), or 15 IRQs (Serial IRQ), 3 DMA channels, and 480 re-locatable address
Capable of ISA Bus IRQ Sharing
Comply with Microsoft PC 97 Hardware Design Guide
Support DPM (Device Power Management), ACPI
Report ACPI status interrupt by SCI signal from SCI pin, serial IRQ IRQSER pin, or IRQ A~H pins
Single 24MHz/48MHZ clock input
FDC:
Compatible with IBM PC AT disk drive systems
Variable write pre-compensation with track selectable capability
DMA enable logic
Supports floppy disk drives and tape drives
Detects all overrun and underrun conditions
Built-in address mark detection circuit to simplify the read electronics
FDD anti-virus functions with software write protect and FDD write enable signal (write data signal
was forced to be inactive)
Supports up to four 3.5-inch or 5.25-inch floppy disk drives
Completely compatible with industry standard 82077
360K/720K/1.2M/1.44M/2.88M format;250K, 300K, 500K, 1M, 2M bps data transfer rate
Supports vertical recording format
Support 3-mode FDD, and its Win95 driver
16-byte data FIFOs
UART:
Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
MIDI compatible
Fully programmable serial-interface characteristics:
5, 6, 7 or 8-bit characters
Even, odd or no parity bit generation/detection
1, 1.5 or 2 stop bits generation
Internal diagnostic capabilities:
Loop-back controls for communications link fault isolation
Break, parity, overrun, framing error simulation
Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1)
Maximum baud rate is up to 921k bps for 14.768MHz and 1.5M bps for 24MHz
Publication Release Date: March 1998
- 2 - Version 0.61

12 Page





SeitenGesamt 30 Seiten
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