Datenblatt-pdf.com


PCF8598C-2T02 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF8598C-2T02
Beschreibung 1024 8-bit CMOS EEPROM with I2C-bus interface
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 21 Seiten
PCF8598C-2T02 Datasheet, Funktion
PCF8598C-2
1024 × 8-bit CMOS EEPROM with I2C-bus interface
Rev. 06 — 22 October 2004
Product data
1. Description
The PCF8598C-2 is a floating gate Electrically Erasable Programmable Read Only
Memory (EEPROM) with 8 kbits (1024 × 8-bit) non-volatile storage. By using an
internal redundant storage code, it is fault tolerant to single bit errors. This feature
dramatically increases the reliability compared to conventional EEPROMs. Power
consumption is low due to the full CMOS technology used. The programming voltage
is generated on-chip, using a voltage multiplier.
Data bytes are received and transmitted via the serial I2C-bus. Up to two
PCF8598C-2 devices may be connected to the I2C-bus. Chip select is accomplished
by one address input (A2).
Timing of the E/W cycle is carried out internally, thus no external components are
required. Programming Time Control (PTC), Pin 7, must be connected to either VDD
or left open-circuit. There is an option of using an external clock for timing the length
of an E/W cycle.
2. Features
s Low power CMOS:
x 2.0 mA maximum operating current
x maximum standby current 10 µA (at 6.0 V), typical 4 µA
s Non-volatile storage of 8 kbits organized as 1024 × 8-bit
s Single supply with full operation down to 2.5 V
s On-chip voltage multiplier
s Serial input/output I2C-bus
s Write operations:
x byte write mode
x 8-byte page write mode (minimizes total write time per byte)
s Read operations:
x sequential read
x random read
s Internal timer for writing (no external components)
s Internal power-on reset
s 0 kHz to 100 kHz clock frequency
s High reliability by using a redundant storage code
s Endurance: 1,000,000 Erase/Write (E/W) cycles at Tamb = 22 °C
s 10 years non-volatile data retention time






PCF8598C-2T02 Datasheet, Funktion
Philips Semiconductors
PCF8598C-2
1024 × 8-bit CMOS EEPROM with I2C-bus interface
8. Functional description
8.1 I2C-bus protocol
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The
serial bus consists of two bidirectional lines; one for data signals (SDA), and one for
clock signals (SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is
HIGH. Changes in the data line while the clock line is HIGH will be interpreted as
control signals.
8.1.1 Bus conditions
The following bus conditions have been defined:
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — A change in the state of the data line, from HIGH-to-LOW,
while the clock is HIGH, defines the START condition.
Stop data transfer — A change in the state of the data line, from LOW-to-HIGH,
while the clock is HIGH, defines the STOP condition.
Data valid — The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
8.1.2 Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP
condition. The number of the data bytes, transferred between the START and STOP
conditions is limited to 7 bytes in the E/W mode and 8 bytes in the Page E/W mode.
Data transfer is unlimited in the read mode. The information is transmitted in bytes
and each receiver acknowledges with a ninth bit.
Within the I2C-bus specifications, a standard-speed mode (100 kHz clock rate) and a
fast-speed mode (400 kHz clock rate) are defined. The PCF8598C-2 operates in only
the standard-speed mode.
By definition, a device that sends a signal is called a ‘transmitter’, and the device
which receives the signal is called a ‘receiver’. The device which controls the signal is
called the ‘master’. The devices that are controlled by the master are called ‘slaves’.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level,
put on the bus by the transmitter. The master generates an extra acknowledge related
clock pulse. The slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte.
9397 750 14219
Product data
Rev. 06 — 22 October 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6 of 21

6 Page









PCF8598C-2T02 pdf, datenblatt
Philips Semiconductors
PCF8598C-2
1024 × 8-bit CMOS EEPROM with I2C-bus interface
SDA
t BUF
t LOW
SCL P
S
t HD;STA
t r t HD;DAT
P = STOP condition; S = START condition.
Fig 9. Timing requirements for the I2C-bus.
tf
t HIGH
t SU;DAT
t HD;STA
S
t SU;STA
MBA705
P
t SU;STO
12. Write cycle limits
Table 9: Write cycle limits
Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either VSS or VDD.
Symbol Parameter
Conditions
Min Typ Max
E/W cycle timing
tE/W E/W cycle time
internal oscillator
external clock
7
4 10
Endurance
NE/W
E/W cycle per byte
Tamb = 40 to +85 °C
Tamb = 22 °C
100 000
−−
1000000
13. External clock timing
Unit
ms
ms
cycles
cycles
PTC
SDA
SCL
Fig 10. One byte E/W cycle.
td t r t HIGH t f t LOW
1
2
STOP
257
MBA697
9397 750 14219
Product data
Rev. 06 — 22 October 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12 of 21

12 Page





SeitenGesamt 21 Seiten
PDF Download[ PCF8598C-2T02 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
PCF8598C-2T021024 8-bit CMOS EEPROM with I2C-bus interfaceNXP Semiconductors
NXP Semiconductors

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche