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Número de pieza | W83194R-81 | |
Descripción | 100MHZ CLOCK FOR SIS CHIPSET | |
Fabricantes | Winbond | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de W83194R-81 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
No Preview Available ! W83194R-81
100MHZ CLOCK FOR SIS CHIPSET
1.0 GENERAL DESCRIPTION
The W83194R-81 is a Clock Synthesizer for SiS chipset. W83194R-81 provides all clocks required
for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium and also provides 16
different frequencies of CPU clocks frequency setting. All clocks are externally selectable with
smooth transitions. The W83194R-81 makes SDRAM in synchronous or asynchronous frequency
with CPU clocks.
The W83194R-81 provides I2C serial bus interface to program the registers to enable or disable each
clock outputs and W83194R-81 provides the 0.25%, 0.5% center type spread spectrum to reduce
EMI.
The W83194R-81 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
• Supports Pentium™, Pentium™ Pro, AMD and Cyrix CPUs with I2C.
• 3 CPU clocks
• 13 SDRAM clocks for 3 DIMMs
• 6 PCI synchronous clocks.
• Optional single or mixed supply:
(Vdd = Vddq4=Vddq3 = Vddq2b = 3.3V, Vddq2=2.5V) or
(Vdd = Vddq4=Vddq3 = 3.3V, Vddq2=Vdq2b = 2.5V)
• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
• SDRAM frequency synchronous or asynchronous to CPU clocks
• Smooth frequency switch with selections from 66 to 133mhz(including 90MHz)
• I2C 2-Wire serial interface and I2C read back
• 0.25%, 0.5% center type spread spectrum to reduce EMI
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• MODE pin for power Management
• 48 MHz for USB
• 24 MHz for super I/O
• 48-pin SSOP package
Publication Release Date: Dec. 1998
- 1 - Revision 0.20
1 page W83194R-81
5.5 Power Pins
SYMBOL
Vdd
Vddq2
Vddq2b
Vddq3
Vddq4
Vss
PRELIMINARY
PIN
1
48
42
19, 30, 36
6,14
3,9,16,22,27,
33,39,45
FUNCTION
Power supply for REF0 crystal and core logic.
Power supply for REF1,IOAPIC output, 2.5V.
Power supply for REF2, CPUCLK[0:2], either 2.5V or
3.3V.
Power supply for SDRAM and 48/24MHz outputs.
Power supply for PCICLK outputs.
Circuit Ground.
6.0 FREQUENCY SELECTION BY HARDWARE
SD_SEL
FS2
FS1 FS0
CPU
(MHz)
SDRAM
(MHz)
0
0
0
0
66.70
100.05
0 0 0 1 90 90
0
0
1
0
95.25
63.4
0
0
1
1
100.2
66.8
0 1 0 0 100 75
0 1 0 1 112 74.7
0 1 1 0 124 82.7
0
1
1
1
133.3
88.9
1 0 0 0 66.8 66.8
1 0 0 1 75 75
1 0 1 0 83.3 83.3
1
0
1
1
95.25
95.25
1
1
0
0
100.2
100.2
1 1 0 1 112 112
1 1 1 0 124 124
1
1
1
1
133.3
133.3
PCI
(MHz)
33.35
30
31.7
33.4
30
37.3
31
33.3
33.4
30
33.32
31.7
33.4
37.3
31
33.3
REF (MHz)
IOAPIC
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Publication Release Date: Dec. 1998
- 5 - Revision 0.20
5 Page W83194R-81
PRELIMINARY
8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7 1 - Reserved
6 1 25 24/14MHz(Active / Inactive)
5 1 26 48MHz(Active / Inactive)
4 1 15 SDRAM12 (Active / Inactive)
3 1 17 SDRAM11 (Active / Inactive)
2 1 18 SDRAM10 (Active / Inactive)
1 1 20 SDRAM9 (Active / Inactive)
0 1 21 SDRAM8 (Active / Inactive)
8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7 1 - Reserved
6 - - Latched FS2#
5 1 - Reserved
4 1 47 IOAPIC (Active / Inactive)
3 - - Latched SD_SEL
2 1 44 REF2 (Active / Inactive)
1 1 46 REF1 (Active / Inactive)
0 1 2 REF0 (Active / Inactive)
8.3.7 Register 6: Winbond Chip ID Register (Read Only)
Bit @PowerUp Pin
7 0 - Winbond Chip ID
6 1 - Winbond Chip ID
5 0 - Winbond Chip ID
4 1 - Winbond Chip ID
3 0 - Winbond Chip ID
2 1 - Winbond Chip ID
1 0 - Winbond Chip ID
0 0 - Winbond Chip ID
Description
- 11 -
Publication Release Date: Dec. 1998
Revision 0.20
11 Page |
Páginas | Total 18 Páginas | |
PDF Descargar | [ Datasheet W83194R-81.PDF ] |
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