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W83194R-58 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83194R-58
Beschreibung 100 MHZ AGP CLOCK FOR VIA CHIPSET
Hersteller Winbond
Logo Winbond Logo 




Gesamt 19 Seiten
W83194R-58 Datasheet, Funktion
Preliminary W83194R-37/-58
100 MHZ AGP CLOCK FOR VIA CHIPSET
1.0 GENERAL DESCRIPTION
The W83194R-37/-58 is a Clock Synthesizer for VIA chipset. W83194R-37 provides all clocks
required for high-speed RISC or CISC microprocessor such as Intel PentiumPro, AMD or Cyrix. Eight
different frequencies of CPU, W83194R-58 provides all clocks required for high-speed RISC or CISC
microprocessor such as Intel PentiumII and also provides 16 different frequencies of CPU clocks by
software setting (additional register0 bit2). AGP and PCI clocks are externally selectable with smooth
transitions. The W83194R-37/-58 provides AGP clocks especially for clone chipset, and makes
SDRAM in synchronous frequency with CPU or AGP clocks.
The W83194R-37/-58 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce
EMI.
The W83194R-37/-58 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1V /nS slew rate into 20 pF loads as
maintaining 50 ±5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide
better than 0.5V /nS slew rate.
2.0 FEATURES
Supports Pentium, PentiumPro, PentiumII, AMD and Cyrix CPUs with I2C.
4 CPU clocks
12 SDRAM clocks for 3 DIMs
Two AGP clocks
6 PCI synchronous clocks.
Optional single or mixed supply:
(VDD = VDDq3 = VDDq2 = VDDq2b = 3.3V) or (VDD = VDDq3 = VDDq2 = 3.3V, VDDq2b = 2.5V)
Skew form CPU to PCI clock -1 to 4 nS, center 2.6 nS, AGP to CPU sync. skew 0 nS (250 pS)
SDRAM frequency synchronous to CPU or AGP clocks
Smooth frequency switch with selections from 60 to 100 MHz CPU (-37) and 66 to 150 MHz (-58)
I2C 2-Wire serial interface and I2C read back
±0.5% or ±1.5% (-37) and 0.25%, 0.5% (-58) center type spread spectrum to reduce EMI
Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal)
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
Packaged in 48-pin SSOP
Publication Release Date: April 1999
- 1 - Revision A1






W83194R-58 Datasheet, Funktion
Preliminary W83194R-37/-58
8.0 FUNCTION DESCRIPTION
8.1 Power Management Functions
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 mS for the VCO to stabilize prior to enabling clock outputs to assure
correct pulse widths. When MODE = 0, pins 18 and 17 are inputs (PCI_STOP#), (CPU_STOP#),
when MODE = 1, these functions are not available. A particular clock could be enabled as both the 2-
wire serial control interface and one of these pins indicate that it should be enabled.
The W83194R-37/-58 may be disabled in the low state according to the following table in order to
reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on
transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP#
0
0
1
1
PCI_STOP#
0
1
0
1
CPU & AGP
Low
Low
Running
Running
PCI
Low
Running
Low
Running
OTHER CLKs
Running
Running
Running
Running
XTAL & VCOs
Running
Running
Running
Running
8.2 2-Wire I2C Control Interface
The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83194R-37/-58 initializes with default register settings, and then it optional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA
while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-
high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data
is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code
checking [0000 0000], and byte count checking. After successful reception of each byte, an
acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to
write to internal I2C registers after the string of data. The sequence order is as follows:
Bytes sequence order for I2C controller:
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when read back the data sequence is as follows:
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack Byte 1
Ack
Byte2, 3, 4...
until Stop
-6-

6 Page









W83194R-58 pdf, datenblatt
Preliminary W83194R-37/-58
9.3 DC Characteristics
VDDq2 = VDD = VDDq3 = 3.3V ±5%, VDDq2b = 2.375V~2.9V, TA = 0 °C to +70 °C
PARAMETER
SYM. MIN. TYP. MAX. UNITS TEST CONDITIONS
Input Low Voltage
VIL
0.8 Vdc
Input High Voltage
VIH 2.0
Vdc
Input Low Current
IIL
-66 µA
Input High Current
IIH
5 µA
Output Low Voltage
IOL = 4 mA
VOL
0.4 Vdc All outputs
Output High Voltage
IOH = 4 mA
VOH 2.4
Vdc All outputs using 3.3V
power
Tri-State leakage Current IOZ
10 µA
Dynamic Supply Current
for VDD + VDDq3
IDD3
mA CPU = 66.6 MHz
PCI = 33.3 MHz with load
Dynamic Supply Current
for VDDq2 + VDDq2b
IDD2
mA Same as above
CPU Stop Current for
VDD + VDDq3
ICPUS3
mA Same as above
CPU Stop Current for
VDDq2 + VDDq2b
ICPUS2
mA Same as above
PCI Stop Current for VDD
+ VDDq3
IPD3
mA
9.4 Buffer Characteristics
9.4.1 Type 1 Buffer for CPU (0:3)
PARAMETER
Pull-up Current Min.
Pull-up Current Max.
Pull-down Current Min.
Pull-down Current Max.
Rise/Fall Time Min.
Between 0.4V and 2.0V
Rise/Fall Time Max.
Between 0.4V and 2.0V
SYMBOL
IOH (min.)
IOH (max.)
IOL (min.)
IOL (max.)
TRF (min.)
TRF (max.)
MIN.
-27
0.4
TYP.
MAX.
-27
27
1.6
UNITS
mA
mA
mA
mA
nS
TEST CONDITIONS
Vout = 1.0V
Vout = 2.0V
Vout = 1.2V
Vout = 0.3V
10 pF Load
nS 20 pF Load
- 12 -

12 Page





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