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W83194R-39A Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83194R-39A
Beschreibung 100MHZ 3-DIMM CLOCK
Hersteller Winbond
Logo Winbond Logo 




Gesamt 21 Seiten
W83194R-39A Datasheet, Funktion
W83194R-39/-39A
1.0 GENERAL DESCRIPTION
100MHZ 3-DIMM CLOCK
The W83194R-39/-39A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel Pentium II. W83194R-39 provides eight different frequency of
CPU and PCI clocks and W83194R-39A provides sixteen CPU/PCI frequencies which are externally
selectable with smooth transitions. W83194R-39/-39A also provides 13 SDRAM clocks controlled by
the none-delay buffer_in pin.
The W83194R-39/-39A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. Spread spectrum built in at ¡Ó0.5% or ¡Ó0.25% to reduce EMI. Programmable stopping
individual clock outputs and frequency selection through I2C interface. The device meets the
Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after
power-up. It is not recommend to use the dual function pin for the slots(ISA, PCI, CPU, DIMM). The
add on cards may have a pull up or pull down.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports PentiumII CPU with I2C.
2 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMs
6 PCI synchronous clocks
One IOAPIC clock for multiprocessor support
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
< 250ps skew among CPU and SDRAM clocks
< 250ps skew among PCI clocks
< 5ns propagation delay SDRAM from buffer input
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 50 MHz to 133 MHz CPU
I2C 2-Wire serial interface and I2C read back
Publication Release Date: May 1998
- 1 - Revision 0.20






W83194R-39A Datasheet, Funktion
W83194R-39/-39A
PRELIMINARY
6.0 FREQUENCY SELECTION
6.1 Frequency table of W83194R-39
FS2
FS1
FS0 CPU,SDRAM (MHz)
PCI (MHz)
000
50 25(CPU/2)
001
75 37.5(CPU/2)
010
83.3 41.65(CPU/2)
011
66.8 33.4(CPU/2)
100
103 34.3(CPU/3)
101
112 37.33(CPU/3)
110
133 33.25(CPU/4)
111
100.2
33.3(CPU/3)
6.2 Frequency table of W83194R-39A
FS3=0
CPU,SDRAM (MHz)
PCI (MHz)
FS2 FS1
00
00
01
01
10
10
11
11
FS3=1
FS2 FS1
00
00
01
01
10
10
11
11
FS0
0
1
0
1
0
1
0
1
FS0
0
1
0
1
0
1
0
1
124
75
83.3
66.8
103
112
133
100.3
CPU,SDRAM (MHz)
120
115
110
105
140
150
124
133
41.33(CPU/3)
37.5(CPU/2)
41.65(CPU/2)
33.4(CPU/2)
34.3(CPU/3)
37.33(CPU/3)
44.33(CPU/3)
33.3(CPU/3)
PCI (MHz)
40.00(CPU/3)
38.33(CPU/3)
36.67(CPU/3)
35.00(CPU/3)
35.00(CPU/4)
37.50(CPU/4)
31.00(CPU/4)
33.25(CPU/4)
REF,IOAPIC (MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
REF,IOAPIC
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
REF,IOAPIC
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Publication Release Date: May 1998
- 6 - Revision 0.20

6 Page









W83194R-39A pdf, datenblatt
W83194R-39/-39A
8.3.5 Register 4: Reserved Register (1 = enable, 0 = Stopped)
Bit @PowerUp Pin
Description
7 1 - Reserved
6 1 - Reserved
5 1 - Reserved
4 1 - Reserved
3 1 - Latched FS1#
2 1 - Reserved
1 1 - Reserved
0 1 - Reserved
PRELIMINARY
8.3.6 Register 5: Peripheral Control (1 = enable, 0 = Stopped)
Bit @PowerUp Pin
Description
7 1 - Reserved
6 1 - Reserved
5 1 - Reserved
4 1 47 IOAPIC (Active / Inactive)
3 1 - Reserved
2 1 - Reserved
1 1 46 REF1 (Active / Inactive)
0 1 2 REF0 (Active / Inactive)
NOTE:
1.Inactive means outputs are held LOW and are disabled from switching.
2.Latched Frequency Selects(FS#) will be inverted logic load of the input frequency select pin
conditions.
- 12 -
Publication Release Date: May 1998
Revision 0.20

12 Page





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