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PDF W83194BR-C Data sheet ( Hoja de datos )
| Número de pieza | W83194BR-C | |
| Descripción | 200MHZ CLOCK FOR CAMINO CHIPSET | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W83194BR-C
200MHZ CLOCK FOR CAMINO CHIPSET
1.0 GENERAL DESCRIPTION
The W83194BR-C is a Clock Synthesizer for Intel Camino 820 chipset. W83194BR-C provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable
with smooth transitions.
The W83194BR-C provides I2C serial bus interface to program the registers to enable or disable each
clock outputs and provides 0.5% and 0.75% center type spread spectrum to reduce EMI.
The W83194BR-C accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU
CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5%
duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns
slew rate.
2.0 PRODUCT FEATURES
• 2 CPU clock outputs
• One CPU/2 output as reference input to DRCG
• 3 3V66 clock outputs
• 3 IOAPIC clock outputs
• 8 PCI synchronous clocks.
• Optional single or mixed supply:
(VddQ2 = VddQ3 = 3.3V or VddQ3=3.3V, VddQ2=2.5V)
• CPU to 3V66 offset .0 to 1.5 ns
• 3V66 to PCI offset 1.5 to 4.0 ns
• Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns
• Smooth frequency switch with selections from 66.8 to 200MHz
• I2C 2-Wire serial interface and I2C read back
• 0.5% and 0.75% center type spread spectrum
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• 48 MHz pins for USB
• 24 MHz for super I/O
• 48-pin SSOP package
Publication Release Date: Dec. 1999
- 1 - Revision 0.40
1 page  
W83194BR-C
PRELIMINARY
5.0 Frequency Selection by Hardware
IOAPIC
FS4 FS3 FS2 FS1 FS0 CPU(MHz) CPU/2 3V66/CPU 3V66(MHz) PCI(MHz)
(MHz)
0 0 0 0 0 133.90 66.95
0.50
66.95
33.48 16.74
0 0 0 0 1 128.50 64.25
0.50
64.25
32.13 16.06
0 0 0 1 0 124.00 62.00
0.67
82.67
41.34 20.67
00011
66.80
33.40
1.00
66.80
33.40 16.70
0 0 1 0 0 120.00 60.00
0.67
80.00
40.00 20.00
0 0 1 0 1 114.00 57.00
0.67
76.00
38.00 19.00
0 0 1 1 0 105.00 52.50
0.67
70.00
35.00 17.50
0 0 1 1 1 100.20 50.10
0.67
66.80
33.40 16.70
0 1 0 0 0 160.00 80.00
0.50
80.00
40.00 20.00
0 1 0 0 1 155.00 77.50
0.50
77.50
38.75 19.38
0 1 0 1 0 152.50 76.25
0.50
76.25
38.13 19.06
0 1 0 1 1 150.00 75.00
0.50
75.00
37.50 18.75
0 1 1 0 0 148.00 74.00
0.50
74.00
37.00 18.50
0 1 1 0 1 143.00 71.50
0.50
71.50
35.75 17.88
0 1 1 1 0 138.00 69.00
0.50
69.00
34.50 17.25
0 1 1 1 1 133.30 66.65
0.50
66.65
33.33 16.66
1 0 0 0 0 100.90 50.45
0.50
50.45
25.23 12.61
1 0 0 0 1 109.00 54.50
0.67
72.67
36.34 18.17
1 0 0 1 0 116.00 58.00
0.67
77.34
38.67 19.33
1 0 0 1 1 122.00 61.00
0.50
61.00
30.50 15.25
1 0 1 0 0 126.00 63.00
0.50
63.00
31.50 15.75
1 0 1 0 1 130.00 65.00
0.50
65.00
32.50 16.25
1 0 1 1 0 135.00 67.50
0.50
67.50
33.75 16.88
1 0 1 1 1 140.00 70.00
0.50
70.00
35.00 17.50
1 1 0 0 0 145.00 72.50
0.50
72.50
36.25 18.13
1 1 0 0 1 159.00 79.50
0.50
79.50
39.75 19.88
1 1 0 1 0 162.00 81.00
0.50
81.00
40.50 20.25
1 1 0 1 1 165.00 82.50
0.50
82.50
41.25 20.63
1 1 1 0 0 168.00 84.00
0.50
84.00
42.00 21.00
1 1 1 0 1 171.00 85.50
0.50
85.50
42.75 21.38
1 1 1 1 0 174.00 87.00
0.50
87.00
43.50 21.75
1 1 1 1 1 180.00 90.00
0.50
90.00
45.00 22.50
Publication Release Date: Dec. 1999
- 5 - Revision 0.40
5 Page 
W83194BR-C
6.10 Register 9: M/N Program Register and 3V66 Divisor
Bit @PowerUp Pin
Description
7 0 - N value bit 8
6 0 - 3V66 divisor 00: CPU/2 ; 01: CPU/1.5
5 0 - 3V66 divisor 10: CPU/1 ; 11: CPU/3
4 0 - M value bit 4
3 0 - M value bit 3
2 0 - M value bit 2
1 0 - M value bit 1
0 0 - M value bit 0
6.11 Register 10: M/N Program Register
Bit @PowerUp Pin
7 0 - N value bit 7
6 0 - N value bit 6
5 0 - N value bit 5
4 0 - N value bit 4
3 0 - N value bit 3
2 0 - N value bit 2
1 0 - N value bit 1
0 0 - N value bit 0
Description
6.12 Register 11: Divisor Register
Bit @PowerUp Pin
Description
7 1 - Spread spectrum up count[0:3]
6 1 - Spread spectrum up count[0:3]
5 1 - Spread spectrum up count[0:3]
4 1 - Spread spectrum up count[0:3]
3 1 - Spread spectrum down count[0:3]
2 1 - Spread spectrum down count[0:3]
1 1 - Spread spectrum down count[0:3]
0 1 - Spread spectrum down count[0:3]
PRELIMINARY
- 11 -
Publication Release Date: Dec. 1999
Revision 0.40
11 Page | ||
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