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W83193R-04 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83193R-04
Beschreibung 83.3 MHZ 3-DIMM CLOCK
Hersteller Winbond
Logo Winbond Logo 




Gesamt 18 Seiten
W83193R-04 Datasheet, Funktion
Preliminary W83193R-02/-04/-04A
83.3 MHZ 3-DIMM CLOCK
1.0 GENERAL DESCRIPTION
The W83193R-02/-04/-04A is a Main board Clock Synthesizer which provides all clocks required for
high-speed RISC or CISC microprocessor such as Intel PentiumPro, PentiumII, AMD or Cyrix. Eight
different frequency of CPU and PCI clocks are externally selectable with smooth transitions.
The W83193R-02/-04/-04A also provides I2C serial bus interface to program the registers to enable
or disable each clock outputs and choose the 0.5% or 1.5% center type spread spectrum.
The W83193R-02/-04/-04A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1V /nS slew rate
into 30 pF loads. CPU CLOCK outputs typically provide better than 1V /nS slew rate into 20 pF loads
as maintaining 50 ±5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide
better than 0.5V /nS slew rate.
2.0 FEATURES
Supports Pentium, PentiumPro, PentiumII, AMD and Cyrix CPUs with I2C.
4 CPU clocks
12 SDRAM clocks for 3 DIMs.
7 PCI synchronous clocks.
One IOAPIC clock for multiprocessor support.
Optional single or mixed supply:
(VDD = VDDq3 = VDDq2 = VDDq2b = 3.3V) or (VDD = VDDq3 = 3.3V, VDDq2 = VDD2b = 2.5V)
< 250 pS skew among CPU and SDRAM clocks.
< 250 pS skew among PCI clocks.
Smooth frequency switch with selections from 50 MHz to 83.3 MHz CPU. (W83193R-04)
Smooth frequency switch with selections from 50 MHz to 112 MHz CPU. (W83193R-04A)
I2C 2-Wire serial interface and I2C read back.
Spread spectrum function to reduce EMI.
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal)
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
Packaged in 48-pin SSOP
Publication Release Date: April 1999
- 1 - Revision A1






W83193R-04 Datasheet, Funktion
Preliminary W83193R-02/-04/-04A
The W83193R-02/-04/-04A may be disabled in the low state according to the following table in order
to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period
on transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP#
0
0
1
1
PCI_STOP#
0
1
0
1
CPU
Low
Low
Running
Running
PCI
Low
Running
Low
Running
OTHER CLKs
Running
Running
Running
Running
XTAL & VCOs
Running
Running
Running
Running
8.2 2-Wire I2C Control Interface
The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83193R-02/-04/-04A initializes with default register settings, and then it's optional to use the 2-wire
control interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA
while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-
high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data
is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking. After successful
reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip.
Controller can start to write to internal I2C registers after the string of data. The sequence order is as
follows:
Bytes sequence order for I2C controller:
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when read back, the data sequence is as follows:
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack Byte 1
Ack
Byte2, 3, 4...
until Stop
8.3 Serial Control Registers
The pin column lists the affected pin number and the @PowerUp column gives the state at true power
up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte
Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in
these two bytes are considered "don't care", they must be sent and will be acknowledge. After that,
the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
-6-

6 Page









W83193R-04 pdf, datenblatt
Preliminary W83193R-02/-04/-04A
9.4.2 Type 2 Buffer for IOAPIC
PARAMETER
Pull-up Current Min.
Pull-up Current Max.
Pull-down Current Min.
Pull-down Current Max.
Rise/Fall Time Min.
Between 0.7V and 1.7V
Rise/Fall Time Max.
Between 0.7V and 1.7V
SYMBOL
IOH (min.)
IOH (max.)
IOL (min.)
IOL (max.)
TRF (min.)
TRF (max.)
MIN.
0.4
TYP. MAX.
-29
28
1.8
UNITS
mA
mA
mA
mA
nS
TEST CONDITIONS
Vout = 1.4V
Vout = 2.7V
Vout = 1.0V
Vout = 0.2V
10 pF Load
nS 20 pF Load
9.4.3 Type 3 Buffer for REF1, 24 MHz, 48 MHz
PARAMETER
Pull-up Current Min.
Pull-up Current Max.
Pull-down Current Min.
Pull-down Current Max.
Rise/Fall Time Min.
Between 0.8V and 2.0V
Rise/Fall Time Max.
Between 0.8V and 2.0V
SYMBOL
IOH (min.)
IOH (max.)
IOL (min.)
IOL (max.)
TRF (min.)
MIN.
-29
29
1.0
TRF (max.)
TYP.
MAX.
-23
UNITS
mA
mA
mA
mA
nS
TEST CONDITIONS
Vout = 1.0V
Vout = 3.135V
Vout = 1.95V
Vout = 0.4V
10 pF Load
4.0 nS 20 pF Load
9.4.4 Type 4 Buffer for REF0 and SDRAM (0:11)
PARAMETER
SYMBOL MIN. TYP.
Pull-up Current Min.
Pull-up Current Max.
Pull-down Current Min.
Pull-down Current Max.
Rise/Fall Time Min.
Between 0.8V and 2.0V
Rise/Fall Time Max.
Between 0.8V and 2.0V
IOH (min.)
IOH (max.)
IOL (min.)
IOL (max.)
TRF (min.)
0.5
TRF (max.)
MAX.
-46
53
1.3
UNITS
mA
mA
mA
mA
nS
TEST
CONDITIONS
Vout = 1.65V
Vout = 3.135V
Vout = 1.65V
Vout = 0.4V
20 pF Load
nS 30 pF Load
- 12 -

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