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W78LE51-24 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W78LE51-24
Beschreibung 8-BIT MTP MICROCONTROLLER
Hersteller Winbond
Logo Winbond Logo 




Gesamt 21 Seiten
W78LE51-24 Datasheet, Funktion
Preliminary W78LE51
8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78LE51 is an 8-bit microcontroller which can accommodate a wide supply voltage range with
low power consumption. The instruction set for the W78LE51 is fully compatible with the standard
8051. The W78LE51 contains an 4K bytes MTP ROM (Multiple-Time Programmable ROM); a 128
bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; two
16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported
by seven sources two-level interrupt capability. To facilitate programming and verification, the MTP-
ROM inside the W78LE51 allows the program memory to be programmed and read electronically.
Once the code is confirmed, the user can protect the code for security.
The W78LE51 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 2.4V to 5.5V
128 bytes of on-chip scratchpad RAM
4 KB electrically erasable/programmable MTP-ROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
Two 16-bit timer/counters
One full duplex serial port(UART)
Watchdog Timer
seven sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
DIP 40: W78LE51-24
PLCC 44: W78LE51P-24
PQFP 44: W78LE51F-24
Publication Release Date: December 1998
- 1 - Revision A1






W78LE51-24 Datasheet, Funktion
Preliminary W78LE51
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space. The
AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from
oscillation circuitry, W78LE51 allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may effect to external crystal operating improperly at high frequency above 24 MHz. The
value of R and C1,C2 may need some adjustment while running at lower gain.
***AUXR - Auxiliary register (8EH)
- - - - - - - AO
AO: Turn off ALE output.
4. Power-off Flag
***PCON - Power control (87H)
-
-
-
POF GF1 GF0
PD
IDL
POF:
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD: Power down mode bit. Set it to enter power down mode.
IDL: Idle mode bit. Set it to enter idle mode.
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog
timer is as a system monitor. This is important in real-time control applications. In case of power
glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is
left unchecked the entire system may crash. The watchdog time-out selection will result in different
time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In
general, software should restart the Watchdog timer to put it into a known state. The control bits that
support the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit: 7 6 5
ENW CLRW WIDL
4
-
3210
- PS2 PS1 PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
-6-

6 Page









W78LE51-24 pdf, datenblatt
Preliminary W78LE51
DC CHARACTERISTICS
VSS = 0V, TA = 25° C, unless otherwise specified.
PARAMETER
SYM.
Operating Voltage
Operating Current
VDD
IDD
Idle Current
IIDLE
Power Down Current
IPWDN
Input Current
P1, P2, P3, P4
Input Current
RST
Input Leakage Current
P0, EA
Logic 1 to 0 Transition
Current
P1, P2, P3, P4
Input Low Voltage
P0, P1, P2, P3, P4, EA
Input Low Voltage
RST[*1]
Input Low Voltage
XTAL1 [*3]
Input High Voltage
P0, P1, P2, P3, P4, EA
Input High Voltage
RST[*1]
Input High Voltage
XTAL1 [*3]
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage
P0, ALE, PSEN [*2]
Sink Current
P1, P2, P3, P4
IIN1
IIN2
ILK
ITL
[*4]
VIL1
VIL2
VIL3
VIH1
VIH2
VIH3
VOL1
VOL2
ISK1
SPECIFICATION
MIN.
MAX.
2.4 5.5
- 20
-3
-6
- 1.5
- 50
- 20
-50 +10
-10 +300
-10 +10
-500 -
0 0.8
0 0.5
0 0.8
0 0.3
0 0.8
0 0.6
2.4 VDD +0.2
1.4 VDD +0.2
3.5 VDD +0.2
1.7 VDD +0.2
3.5 VDD +0.2
1.6 VDD +0.2
- 0.45
- 0.25
- 0.45
- 0.25
4 12
1.8 5.4
UNIT
TEST CONDITIONS
V
mA No load VDD = 5.5V
mA No load VDD = 2.4V
mA VDD = 5.5V, Fosc = 20 MHz
mA VDD = 2.4V, Fosc = 12 MHz
µA VDD = 5.5V, Fosc = 20 MHz
µA VDD = 2.4V, Fosc = 12 MHz
µA VDD = 5.5V
VIN = 0V or VDD
µA VDD = 5.5V
0 < VIN < VDD
µA VDD = 5.5V
0V < VIN < VDD
µA VDD = 5.5V
VIN = 2.0V
V VDD = 4.5V
V VDD = 2.4V
V VDD = 4.5V
V VDD = 2.4V
V VDD = 4.5V
V VDD = 2.4V
V VDD = 5.5V
V VDD = 2.4V
V VDD = 5.5V
V VDD = 2.4V
V VDD = 5.5V
V VDD = 2.4V
V VDD = 4.5V, IOL = +2 mA
V VDD = 2.4V, IOL = +1 mA
V VDD = 4.5V, IOL = +4 mA
V VDD = 2.4V, IOL = +2 mA
mA VDD = 4.5V, Vin = 0.45V
mA VDD = 2.4V, Vin = 0.45V
- 12 -

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