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W78E52BF-40 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W78E52BF-40
Beschreibung 8-BIT MTP MICROCONTROLLER
Hersteller Winbond
Logo Winbond Logo 




Gesamt 22 Seiten
W78E52BF-40 Datasheet, Funktion
Preliminary W78E52B
8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78E52B is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E52B is fully compatible with the standard 8051.
The W78E52B contains an 8K bytes MTP ROM (Multiple-Time Programmable ROM); a 256 bytes
RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-
bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by
eight sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM
inside the W78E52B allows the program memory to be programmed and read electronically. Once
the code is confirmed, the user can protect the code for security.
The W78E52B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 4.5V to 5.5V
256 bytes of on-chip scratchpad RAM
8 KB electrically erasable/programmable MTP-ROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
Three 16-bit timer/counters
One full duplex serial port(UART)
Watchdog Timer
Eight sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
DIP 40: W78E52B-24/40
PLCC 44: W78E52BP-24/40
PQFP 44: W78E52BF-24/40
Publication Release Date: December 1998
- 1 - Revision A1






W78E52BF-40 Datasheet, Funktion
Preliminary W78E52B
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,
INT3 ).
Example:
P4
MOV
MOV
SETB
CLR
REG 0D8H
P4, #0AH ; Output data "A" through P4.0P4.3.
A, P4
; Read P4 status to Accumulator.
P4.0
; Set bit P4.0
P4.1
; Clear bit P4.1
3. Reduce EMI Emission
Because of on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space. The
AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from
oscillation circuitry, W78E52B allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may affect the external crystal operating improperly at high frequency above 24MHz. The
value of R and C1,C2 may need some adjustment while running at lower gain.
***AUXR - Auxiliary register (8EH)
- - - - - - - AO
AO: Turn off ALE output.
4. Power-off Flag
***PCON - Power control (87H)
-
-
-
POF GF1 GF0
PD
IDL
POF:
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD: Power down mode bit. Set it to enter power down mode.
IDL: Idle mode bit. Set it to enter idle mode.
-6-

6 Page









W78E52BF-40 pdf, datenblatt
Preliminary W78E52B
+5V
A0 to A7
VIL
VIL
VIL
VIL
VIL
VIH
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
Vss
VDD
P0
EA/Vpp
ALE
RST
PSEN
P2
PGM DATA
VCP
VIL
VIH
VIH
A8 to A15
Programming Configuration
+5V
A0 to A7
VIL
VIL
VIL
VIL
VIH
VIL
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
Vss
VDD
P0
EA/Vpp
ALE
RST
PSEN
P2
PGM DATA
VCP
VIL
VIH
VIH
A8 to A15
Programming Verification
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
Input Voltage
Operating Temperature
Storage Temperature
SYMBOL
VDDVSS
VIN
TA
TST
MIN.
-0.3
VSS -0.3
0
-55
MAX.
+7.0
VDD +0.3
70
+150
UNIT
V
V
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC CHARACTERISTICS
VCCVSS = 5V ±10%, TA = 25° C, unless otherwise specified.
PARAMETER
SYMBOL TEST CONDITIONS
Operating Voltage
Operating Current
Idle Current
Power Down Current
Input Current
P1, P2, P3
Logical 1-to-0 Transition
Current P1, P2, P3 (*1)
Input Current
RST (*2)
VDD
IDD
IIDLE
IPWDN
IIN1
ITL
IIN2
No load VDD = 5.5V
Idle mode VDD = 5.5V
Power-down mode
VDD = 5.5V
VDD = 5.5V
VIN = 0V or VDD
VDD = 5.5V
VIN = 2.0V (*1)
VDD = 5.5V
VIN = VDD
SPECIFICATION
MIN.
MAX.
4.5 5.5
- 20
-6
- 50
-50 +10
-550 -
-10 +300
UNIT
V
mA
mA
µA
µA
µA
µA
- 12 -

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