|
|
Teilenummer | W78C52D |
|
Beschreibung | 8-BIT MICROCONTROLLER | |
Hersteller | Winbond | |
Logo | ||
Gesamt 18 Seiten Preliminary W78C52D
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C52D microcontroller supplies a wider frequency and supply voltage range than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C52 microcontroller
series. The W78C52D contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable
I/O port (Port 4) and two additional external interrupts (INT2 , INT3 ), three 16-bit timer/counters, one
watchdog timer and a serial port. These peripherals are supported by a eight-source, two-level
interrupt capability. There are 256 bytes of RAM and an 8K byte mask ROM for application programs.
The W78C52D microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
• Fully static design
• Supply voltage of 4.5V to 5.5V
• DC-40 MHz operation
• 256 bytes of on-chip scratchpad RAM
• 8K bytes of on-chip mask ROM
• 64K bytes program memory address space
• 64K bytes data memory address space
• Four 8-bit bidirectional ports
• Three 16-bit timer/counters
• One full duplex serial port
• Eight-source, two-level interrupt capability
• One extra 4-bit bit-addressable I/O port
• Two additional external interrupts INT2 / INT3
• Watchdog timer
• EMI reduction mode
• Built-in power management
• Code protection
• Packages:
− DIP 40: W78C52D-24/40
− PLCC 44: W78C52DP-24/40
− QFP 44: W78C52DF-24/40
Publication Release Date: December 1998
- 1 - Revision A1
Preliminary W78C52D
deglitch the reset line when the W78C52D is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts
INT2 , INT3 have been added to either the PLCC or QFP package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
***XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INTERRUPT
SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
Timer/Counter 2
External Interrupt 2
External Interrupt 3
VECTOR
ADDRESS
03H
0BH
13H
1BH
23H
2BH
33H
3BH
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
0 (highest)
IE.0
1 IE.1
2 IE.2
3 IE.3
4 IE.4
5 IE.5
6 XICON.2
7 (lowest)
XICON.6
INTERRUPT
TYPE
EDGE/LEVEL
TCON.0
-
TCON.2
-
-
-
XICON.0
XICON.3
-6-
6 Page Preliminary W78C52D
Data Read Cycle
PARAMETER
SYMBOL
ALE Low to RD Low
TDAR
RD Low to Data Valid
TDDA
Data Hold from RD High
TDDH
Data Float from RD High
TDDZ
RD Pulse Width
TDRD
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
MIN.
3 TCP-∆
-
0
0
6 TCP-∆
TYP.
-
-
-
-
6 TCP
MAX.
3 TCP+∆
4 TCP
2 TCP
2 TCP
-
UNIT
nS
nS
nS
nS
nS
NOTES
1, 2
1
2
Data Write Cycle
PARAMETER
SYMBOL MIN.
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
TDAW
TDAD
TDWD
TDWR
3 TCP-∆
1 TCP-∆
1 TCP-∆
6 TCP-∆
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
6 TCP
MAX.
3 TCP+∆
-
-
-
UNIT
nS
nS
nS
nS
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
TPDH
TPDA
MIN.
1 TCP
0
1 TCP
TYP.
-
-
-
MAX.
-
-
-
UNIT
nS
nS
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
- 12 -
12 Page | ||
Seiten | Gesamt 18 Seiten | |
PDF Download | [ W78C52D Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
W78C52D | 8-BIT MICROCONTROLLER | Winbond |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |