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W6811 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W6811
Beschreibung SINGLE-CHANNEL VOICEBAND CODEC
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W6811 Datasheet, Funktion
W6811
SINGLE-CHANNEL VOICEBAND CODEC
(5V Analog, 3V Digital)
www.DataSheet4U.com
Data Sheet
Publication Release Date: September, 2005
- 1 - Revision A12






W6811 Datasheet, Funktion
W6811
6. PIN DESCRIPTION
Pin
Name
Pin VDD* Functionality
No.
VREF
1 A This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be
decoupled to VSSA through a 0.1 μF ceramic decoupling capacitor. No
external loads should be tied to this pin.
RO- 2 A Inverting output of the receive smoothing filter. This pin can typically drive a 2
kΩ load to 1.575 volt peak referenced to the analog ground level.
PAI 3 A This pin is the inverting input to the power amplifier. Its DC level is at the VAG
voltage.
PAO- 4 A Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt
peak referenced to the VAG voltage level.
PAO+ 5 A Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575
Volt peak referenced to the VAG voltage level.
VDDA
6 A Analog power supply. This pin should be decoupled to VSSA with a 0.1μF
ceramic capacitor.
NC 7
Not Connected
VDDD
FSR
8 D Digital power supply. This pin should be decoupled to VSSD with a 0.1μF
ceramic capacitor. For correct operation, VDDD value should always be lower
than VDDA.
9 D 8 kHz Frame Sync input for the PCM receive section. This pin also selects
channel 0 or channel 1 in the GCI and IDL modes. It can also be connected to
the FST pin when transmit and receive are synchronous operations.
PCMR 10 D
PCM input data receive pin. The data needs to be synchronous with the FSR
and BCLKR pins.
BCLKR 11 D
PCM receive bit clock input pin. This pin also selects the interface mode. The
GCI mode is selected when this pin is tied to VSSD. The IDL mode is selected
when this pin is tied to VDDD. This pin can also be tied to the BCLKT when
transmit and receive are synchronous operations.
PUI
MCLK
12 D
13 D
Power up input signal. When this pin is tied to VDDD, the part is powered up.
When tied to VSSD, the part is powered down.
System master clock input. Possible input frequencies are 256 kHz, 512 kHz,
1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better
performance, it is recommended to have the MCLK signal synchronous and
aligned to the FST signal. This is a requirement in the case of 256 and 512
kHz frequencies.
BCLKT 14 D PCM transmit bit clock input pin.
PCMT 15 D
PCM output data transmit pin. The output data is synchronous with the FST
and BCLKT pins.
FST 16 D 8 kHz transmit frame sync input. This pin synchronizes the transmit data
bytes.
Publication Release Date: September, 2005
- 6 - Revision A12

6 Page









W6811 pdf, datenblatt
W6811
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDDD for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface
consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the
first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK
cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after
the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK
after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the
IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not
used for data transmission and also in the time slot of the unused channels. For more timing
information, see the timing section.
7.4.5. System Timing
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz
master clock rates. The system clock is supplied through the master clock input MCLK and can be
derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and an
8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency
versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW for
the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W6811
will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW.
When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the Frame
Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become
low impedance.
Publication Release Date: September, 2005
- 12 -
Revision A12

12 Page





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