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PCF8591 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF8591
Beschreibung 8-bit A/D and D/A converter
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCF8591 Datasheet, Funktion
PCF8591
8-bit A/D and D/A converter
Rev. 7 — 27 June 2013
Product data sheet
1. General description
The PCF8591 is a single-chip, single-supply low-power 8-bit CMOS data acquisition
device with four analog inputs, one analog output and a serial I2C-bus interface. Three
address pins A0, A1 and A2 are used for programming the hardware address, allowing
the use of up to eight devices connected to the I2C-bus without additional hardware.
Address, control and data to and from the device are transferred serially via the two-line
bidirectional I2C-bus.
The functions of the device include analog input multiplexing, on-chip track and hold
function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The
maximum conversion rate is given by the maximum speed of the I2C-bus.
2. Features and benefits
Single power supply
Operating supply voltage 2.5 V to 6.0 V
Low standby current
Serial input and output via I2C-bus
I2C address selection by 3 hardware address pins
Max sampling rate given by I2C-bus speed
4 analog inputs configurable as single ended or differential inputs
Auto-incremented channel selection
Analog voltage range from VSS to VDD
On-chip track and hold circuit
8-bit successive approximation A/D conversion
Multiplying DAC with one analog output.
3. Applications
Supply monitoring
Reference setting
Analog control loops






PCF8591 Datasheet, Funktion
NXP Semiconductors
PCF8591
8-bit A/D and D/A converter
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8.3 D/A conversion
The third byte sent to a PCF8591 device is stored in the DAC data register and is
converted to the corresponding analog voltage using the on-chip D/A converter. This D/A
converter consists of a resistor divider chain connected to the external reference voltage
with 256 taps and selection switches. The tap-decoder switches one of these taps to the
DAC output line (see Figure 5).
The analog output voltage is buffered by an auto-zeroed unity gain amplifier. Setting the
analog output enable flag of the control register switches this buffer amp on or off. In the
active state, the output voltage is held until a further data byte is sent.
The on-chip D/A converter is also used for successive approximation A/D conversion. In
order to release the DAC for an A/D conversion cycle the unity gain amplifier is equipped
with a track and hold circuit. This circuit holds the output voltage while executing the A/D
conversion.
PCF8591
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 27 June 2013
© NXP B.V. 2013. All rights reserved.
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PCF8591 pdf, datenblatt
NXP Semiconductors
PCF8591
8-bit A/D and D/A converter
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
SLAVE
RECEIVER
Fig 13. System configuration
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
mga807
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte
Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered)
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition
Acknowledgement on the I2C-bus is shown in Figure 14.
data output
by transmitter
data output
by receiver
SCL from
master
S
START
condition
1
2
Fig 14. Acknowledgement on the I2C-bus
not acknowledge
acknowledge
89
clock pulse for
acknowledgement
mbc602
9.5 I2C bus protocol
After a START condition, the I2C slave address has to be sent to the PCF8591 device.
PCF8591
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 27 June 2013
© NXP B.V. 2013. All rights reserved.
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