Datenblatt-pdf.com


PCF8579 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF8579
Beschreibung LCD column driver for dot matrix graphic displays
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCF8579 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF8579
LCD column driver for dot matrix
graphic displays
Product specification
Supersedes data of 1996 Oct 25
File under Integrated Circuits, IC12
1997 Apr 01






PCF8579 Datasheet, Funktion
Philips Semiconductors
LCD column driver for dot matrix graphic
displays
Product specification
PCF8579
1997 Apr 01
SDA 1
56 C0
SCL 2
55 C1
SYNC 3
54 C2
CLK 4
53 C3
VSS 5
52 C4
TEST 6
51 C5
SA0 7
50 C6
A3 8
49 C7
A2 9
48 C8
A1 10
47 C9
A0 11
V DD 12
46 C10
45 C11
n.c. 13
44 C12
V 3 14
V 4 15
V LCD 16
PCF8579
43 C13
42 C14
41 C15
C39 17
40 C16
C38 18
39 C17
C37 19
38 C18
C36 20
37 C19
C35 21
36 C20
C34 22
35 C21
C33 23
34 C22
C32 24
33 C23
C31 25
32 C24
C30 26
31 C25
C29 27
30 C26
C28 28
29 C27
MSA918
Fig.2 Pin configuration (VSO56).
6

6 Page









PCF8579 pdf, datenblatt
Philips Semiconductors
LCD column driver for dot matrix graphic
displays
Product specification
PCF8579
7.3 Timing generator
The timing generator of the PCF8579 organizes the
internal data flow from the RAM to the display drivers.
An external synchronization pulse SYNC is received from
the PCF8578. This signal maintains the correct timing
relationship between cascaded devices.
7.4 Column drivers
Outputs C0 to C39 are column drivers which must be
connected to the LCD. Unused outputs should be left
open-circuit.
7.5 Display RAM
The PCF8579 contains a 32 × 40-bit static RAM which
stores the display data. The RAM is divided into 4 banks of
40 bytes (4 × 8 × 40 bits). During RAM access, data is
transferred to/from the RAM via the I2C-bus.
7.6 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
data byte or a series of data bytes to be written into, or read
from, the display RAM, controlled by commands sent on
the I2C-bus.
7.7 Subaddress counter
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage and
retrieval take place only when the contents of the
subaddress counter agree with the hardware subaddress
at pins A0, A1, A2 and A3.
7.8 I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8579 acts as an
I2C-bus slave transmitter/receiver. Device selection
depends on the I2C-bus slave address, the hardware
subaddress and the commands transmitted.
7.9 Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.10 RAM access
There are three RAM ACCESS modes:
Character
Half-graphic
Full-graphic.
These modes are specified by bits G1 and G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.8).
To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.9):
Device subaddress (specified by the DEVICE SELECT
command)
RAM X-address (specified by the LOAD X-ADDRESS
command)
RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
Subsequent data bytes will be written or read according to
the chosen RAM access mode. Device subaddresses are
automatically incremented between devices until the last
device is reached. If the last device has subaddress 15,
further display data transfers will lead to a wrap-around of
the subaddress to 0.
7.11 Display control
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.
The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits
B1 and B0 of the SET START BANK command. This is
shown in Fig.10 This feature is useful when scrolling in
alphanumeric applications.
7.12 TEST pin
The TEST pin must be connected to VSS.
1997 Apr 01
12

12 Page





SeitenGesamt 30 Seiten
PDF Download[ PCF8579 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
PCF8570256 x 8-bit static low-voltage RAM with I2C-bus interfaceNXP Semiconductors
NXP Semiconductors
PCF8570C128 x 8 Bit / 256 x 8 Bit Static Ram with IC Bus InterfacePhilips
Philips
PCF8570P256 x 8-bit static low-voltage RAM with I2C-bus interfaceNXP Semiconductors
NXP Semiconductors
PCF8570T256 x 8-bit static low-voltage RAM with I2C-bus interfaceNXP Semiconductors
NXP Semiconductors
PCF8571128 x 8 Bit / 256 x 8 Bit Static Ram with IC Bus InterfacePhilips
Philips

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche