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Teilenummer | W183-5 |
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Beschreibung | Full Feature Peak Reducing EMI Solution | |
Hersteller | Cypress Semiconductor | |
Logo | ||
Gesamt 8 Seiten W183
Full Feature Peak Reducing EMI Solution
Features
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the out-
put
• Selectable output frequency range
• Single 1.25%, 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz
Crystal Reference Range:................. 28 MHz ≤ Fin ≤ 40 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
Table 1. Modulation Width Selection
SS%
0
1
W183
Output
Fin ≥ Fout ≥ Fin –
1.25%
Fin ≥ Fout ≥ Fin –
3.75%
W183-5
Output
Fin + 0.625% ≥ Fin≥
– 0.625%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
FS2 FS1
00
01
10
11
Frequency Range
28 MHz ≤ FIN ≤ 38 MHz
38 MHz ≤ FIN ≤ 48 MHz
46 MHz ≤ FIN ≤ 60 MHz
58 MHz ≤ FIN ≤ 75 MHz
Pin Configuration
SOIC
XTAL
Input
40 MHz
Max
X1
X2
W183
Spread Spectrum
Output
(EMI suppressed)
FS2
CLKIN or X1
NC or X2
GND
GND
SS%
FS1
1
2
3
4
5
6
7
14 REFOUT
13 OE#
12 SSON#
11 Reset
10 VDD
9 VDD
8 CLKOUT
3.3V or 5.0V
Oscillator or
Reference Input
W183
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 25, 2000, rev.*B
W183
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10%
Parameter
IDD
tON
VIL
VIH
VOL
VOH
IIL
IIH
IOL
IOH
CI
RP
ZOUT
Description
Supply Current
Power Up Time
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
Test Condition
First locked clock cycle after
Power Good
Note 2
Note 2
@ 0.4V, VDD = 5V
@ 2.4V, VDD = 5V
Min.
0.7VDD
2.4
–50
Typ.
30
24
24
500
25
Max.
50
5
Unit
mA
ms
0.15VDD
0.4
50
7
V
V
V
V
µA
µA
mA
mA
pF
kΩ
Ω
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10%
Symbol
Parameter
Test Condition
Min.
fIN
fOUT
fXOSC
tR
tF
tOD
tID
tJCYC
Input Frequency
Output Frequency
Crystal Oscillator Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle
Input Duty Cycle
Jitter, Cycle-to-Cycle
Harmonic Reduction
Input Clock
Spread Off
15-pF load, 0.8V–2.4V
15-pF load, 2.4V–0.8V
15-pF load
fout = 40 MHz, third harmonic
measured, reference board,
15-pF load
28
28
28
40
40
8
Note:
2. Inputs FS2:1 have a pull-up resistor, Input SSON# has a pull-down resistor.
Typ.
2
2
250
Max.
75
75
40
5
5
60
60
300
Unit
MHz
MHz
MHz
ns
ns
%
%
ps
dB
6
6 Page | ||
Seiten | Gesamt 8 Seiten | |
PDF Download | [ W183-5 Schematic.PDF ] |
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