W181 Datasheet PDF - Cypress Semiconductor
| Part Number | W181 | |
| Description | Peak Reducing EMI Solution | |
| Manufacturers | Cypress Semiconductor | |
| Logo |  |
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W181
Features
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the out-
put
• Selectable input to output frequency
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
• Available in 8-pin SOIC (Small Outline Integrated Cir-
cuit) or 14-pin TSSOP (Thin Shrink Small Outline Pack-
age select options only)
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz
Crystal Reference Range.................. 28 MHz ≤ Fin ≤ 40 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3 or 5.0V
XTAL
Input
40 MHz
Max.
X1
X2
W181
Spread Spectrum
Output
(EMI suppressed)
3.3 or 5.0V
Oscillator or
Reference Input
W181
Spread Spectrum
Output
(EMI suppressed)
Peak Reducing EMI Solution
Table 1. Modulation Width Selection
SS%
0
1
W181-01, 02, 03
Output
Fin ≥ Fout ≥ Fin –
1.25%
Fin ≥ Fout ≥ Fin –
3.75%
W181-51, 52, 53
Output
Fin + 0.625% ≥ Fin≥
– 0.625%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
W181 Option#
FS2 FS1
-01, 51
(MHz)
-02, 52
(MHz)
-03, 53
(MHz)
0 0 28 ≤ FIN ≤ 38 28 ≤ FIN ≤ 38
N/A
0 1 38 ≤ FIN ≤ 48 38 ≤ FIN ≤ 48
N/A
1 0 46 ≤ FIN ≤ 60 N/A 46 ≤ FIN ≤ 60
1 1 58 ≤ FIN ≤ 75 N/A 58 ≤ FIN ≤ 75
Pin Configurations
SOIC
CLKIN or X1
NC or X2
GND
SS%
1
2
3
4
8 FS2
7 FS1
6 VDD
5 CLKOUT
CLKIN or X1
NC or X2
GND
SS%
1
2
3
4
8 SSON#
7 FS1
6 VDD
5 CLKOUT
TSSOP
FS2
CLKIN or X1
NC or X2
GND
NC
SS%
NC
1
2
3
4
5
6
7
14 NC
13 NC
12 FS1
11 NC
10 VDD
9 NC
8 CLKOUT
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 21, 2000, rev. *B
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W181
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
VDD, VIN
TSTG
TA
TB
PD
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5%
Parameter
Description
Test Condition
IDD Supply Current
tON Power-Up Time
First locked clock cycle after Power
Good
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
IIL
Input Low Current
Note 1
IIH
Input High Current
Note 1
IOL
Output Low Current
@ 0.4V, VDD = 3.3V
IOH
Output High Current
@ 2.4V, VDD = 3.3V
CI
Input Capacitance
All pins except CLKIN
CI
Input Capacitance
CLKIN pin only
RP Input Pull-Up Resistor
ZOUT
Clock Output Impedance
Note:
1. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
Min.
2.4
2.4
Typ.
18
15
15
6
500
25
Max.
32
5
0.8
0.4
–100
10
7
10
Unit
mA
ms
V
V
V
V
µA
µA
mA
mA
pF
pF
kΩ
Ω
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for W181 electronic component. |
| Information | Total 9 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ W181.PDF Datasheet ] | |
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