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PDF W180 Data sheet ( Hoja de datos )

Número de pieza W180
Descripción Peak Reducing EMI Solution
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! W180 Hoja de datos, Descripción, Manual

W180
Features
Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
• Available in 8-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: .............................. 8 MHz Fin 28 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
3.3V or 5.0V
XTAL
Input
X1
X2
W180
Spread Spectrum
Output
(EMI suppressed)
3.3V or 5.0V
Peak Reducing EMI Solution
Table 1. Modulation Width Selection
SS%
0
1
W180-01, 02, 03
Output
Fin Fout Fin
1.25%
Fin Fout Fin
3.75%
W180-51, 52, 53
Output
Fin + 0.625% Fin
0.625%
Fin + 1.875% Fin
–1.875%
Table 2. Frequency Range Selection
W180 Option#
FS2 FS1
-01, 51
(MHz)
-02, 52
(MHz)
-03, 53
(MHz)
0 0 8 FIN 10 8 FIN 10
N/A
0 1 10 FIN 15 10 FIN 15
N/A
1 0 15 FIN 18 N/A 15 FIN 18
1 1 18 FIN 28 N/A 18 FIN 28
Pin Configurations
SOIC
CLKIN or X1
NC or X2
GND
SS%
1
2
3
4
8 FS2
7 FS1
6 VDD
5 CLKOUT
CLKIN or X1
NC or X2
GND
SS%
1
2
3
4
8 SSON#
7 FS1
6 VDD
5 CLKOUT
Oscillator or
Reference Input
W180
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 21, 2000, rev. *A

1 page




W180 pdf
W180
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
Parameter
Description
VDD, VIN
TSTG
TA
TB
PD
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
0.5 to +7.0
65 to +150
0 to +70
55 to +125
0.5
Unit
V
°C
°C
°C
W
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5%
Parameter
Description
Test Condition
IDD Supply Current
tON Power Up Time
First locked clock cycle after Power
Good
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
IIL
Input Low Current
Note 1
IIH
Input High Current
Note 1
IOL
Output Low Current
@ 0.4V, VDD = 3.3V
IOH
Output High Current
@ 2.4V, VDD = 3.3V
CI Input Capacitance
RP Input Pull-Up Resistor
ZOUT
Clock Output Impedance
Note:
1. Inputs FS2:1& SS% have a pull-up resistor; Input SSON# has a pull-down resistor.
Min.
2.4
2.4
50
Typ.
18
15
15
500
25
Max.
32
5
0.8
0.4
50
7
Unit
mA
ms
V
V
V
V
µA
µA
mA
mA
pF
k
5

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