PDF W170 Data sheet ( Hoja de datos )

Número de pieza	W170
Descripción	Spread Aware/ Frequency Multiplier and Zero Delay Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! W170-01 Spread Aware™, Frequency Multiplier and Zero Delay Buffer Features • Spread Aware™—designed to work with SSFTG reference signals • Two outputs • Configuration options allow various multiplication of the reference frequency, refer to Table 1 to determine the specific option which meets your multiplication needs • Available in 8-pin SOIC package Key Specifications Operating Voltage: ...........................3.3V±5% or 5.0V± 10% Operating Range: .......................20 MHz < fOUT1 < 133 MHz Absolute Jitter: ......................................................... ±500 ps Output to Output Skew: .............................................. 250 ps Propagation Delay: ................................................... ±350 ps Propagation delay is affected by input rise time. Table 1. Configuration Options FBIN FS0 FS1 OUT1 OUT1 0 0 2 X REF OUT1 1 0 4 X REF OUT1 0 1 REF OUT1 1 1 8 X REF OUT2 0 0 4 X REF OUT2 1 0 8 X REF OUT2 0 1 2 X REF OUT2 1 1 16 X REF OUT2 REF 2 X REF REF/2 4 X REF 2 X REF 4 X REF REF 8 X REF Block Diagram Pin Configuration FBIN FS0 ÷Q FS1 External feedback connection to OUT1 or OUT2, not both FBIN IN GND FS0 1 2 3 4 8 OUT2 7 VDD 6 OUT1 5 FS1 IN Reference Input Phase Detector Charge Pump Loop Filter Output Buffer VCO ÷2 Output Buffer OUT1 OUT2 Spread Aware is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 September 28, 1999, rev. ** 1 page W170-01 AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% Parameter Description Test Condition Min Typ Max Unit fIN Input Frequency[1] OUT2 = REF MHz fOUT Output Frequency OUT1 20 133 MHz tR Output Rise Time 0.8V to 2.0V, 15-pF load 3.5 ns tF tICLKR tICLKF tPD Output Fall Time Input Clock Rise Time[2] Input Clock Fall Time[2] FBIN to IN (Reference Input) Skew[3, 4] 2.0V to 0.8V, 15-pF load Note 4 2.5 ns 10 ns 10 ns 300 ps tD Duty Cycle Note 5 40 50 60 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle Note 6 200 ps AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 5V±10% Parameter Description Test Condition Min Typ Max Unit fIN Input Frequency[1] OUT2 = REF MHz fOUT Output Frequency OUT1 20 133 MHz tR Output Rise Time 0.8V to 2.0V, 15-pF load 3.5 ns tF tICLKR tICLKF tPD Output Fall Time Input Clock Rise Time[2] Input Clock Fall Time[2] FBIN to IN (Reference Input) Skew[3, 4] 2.0V to 0.8V, 15-pF load Note 4 2.5 ns 10 ns 10 ns 300 ps tD Duty Cycle Note 7, 8 40 50 60 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle Note 6 200 ps Notes: 1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. Longer input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 4. Skew is measured at 1.4V on rising edges. 5. Duty cycle is measured at 1.4V. 6. Jitter is measured on 133-MHz signal at 1.4V. 7. Duty cycle is measured at 1.4V, 120 MHz. 8. Duty cycle at 133 MHz is 35/65 worst case. Ordering Information Ordering Code W170 Document #: 38-00795 Option -01 Package Name G Package Type 8-pin SOIC (150 mil) 5 5 Page

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