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PCF8573T Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF8573T
Beschreibung Clock/calendar with Power Fail Detector
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 24 Seiten
PCF8573T Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF8573
Clock/calendar with Power Fail
Detector
Product specification
Supersedes data of May 1989
File under Integrated Circuits, IC12
1997 Mar 28






PCF8573T Datasheet, Funktion
Philips Semiconductors
Clock/calendar with Power Fail Detector
Product specification
PCF8573
7.5 Power on/power fail detection
If the voltage VDD VSS1 falls below a certain value the
operation of the clock becomes undefined. Thus a warning
signal is required to indicate that faultless operation of the
clock is not guaranteed. This information is latched in a
flag called POWF (Power Fail) and remains latched after
restoration of the correct supply voltage until a write
procedure with EXECUTE ADDRESS has been received.
The flag POWF can be set by an internally generated
power fail level-discriminator signal for application with
(VDD VSS1) greater than VTH1, or by an externally
generated power fail signal for application with
(VDD VSS1) less than VTH1. The external signal must be
applied to the input PFIN. The input stage operates with
signals of slow rise and fall times. Internally or externally
controlled POWF can be selected by input EXTPF as
shown in Table 2.
Table 2 Power fail selection
EXTPF(1) PFIN(1)
FUNCTION
0 0 power fail is sensed internally
0 1 test mode
1 0 power fail is sensed externally
1 1 no power fail sensed
Note
1. 0 = VSS1 (LOW); 1 = VDD (HIGH).
The external power fail control operates by absence of the
VDD VSS2 supply. Therefore the input levels applied to
PFIN and EXTPF must be within the range of VDDVSS1.
A LOW level at PFIN indicates a power fail. POWF is
readable via the I2C-bus. A power-on reset for the I2C-bus
control is generated on-chip when the supply voltage
VDD VSS2 is less than VTH2.
7.6 Interface level shifters
The level shifters adjust the 5 V operating voltage
(VDD VSS2) of the microcontroller to the internal supply
voltage (VDD VSS1) of the clock/calendar. The oscillator
and counter are not influenced by the VDD VSS2 supply
voltage. If the voltage VDD VSS2 is absent (VDD = VSS2)
the output signal of the level shifter is HIGH because VDD
is the common node of the VDD VSS2 and the VDD VSS1
supplies. Because the level shifters invert the input
signals, the internal circuit behaves as if a LOW signal is
present on the inputs. FSET, SEC, MIN and COMP are
CMOS push-pull output stages. The driving capability of
these outputs is lost when the supply voltage
VDD VSS2 = 0.
1997 Mar 28
6

6 Page









PCF8573T pdf, datenblatt
Philips Semiconductors
Clock/calendar with Power Fail Detector
Product specification
PCF8573
Acknowledgement response of the PCF8573 as slave-receiver is shown in Table 6. Note that data is only associated
with the ‘execute address’ function where C0, C1, C2 = 0, 0, 0.
Table 6 Slave receiver acknowledgement; note 1
MODE POINTER
ACKNOWLEDGE ON BYTE:
BIT 8 C2 C1 C0 BIT 4 B2 B1 B0 ADDRESS MODE POINTER DATA
0 0 0 0 0 X X X yes
0 0 0 0 1 X X X yes
0 0 0 1 X X X X yes
0 0 1 0 X X X X yes
0 0 1 1 X X X X yes
0 1 0 0 X X X X yes
0 1 0 1 X X X X yes
0 1 1 0 X X X X yes
0 1 1 1 X X X X yes
1 X X X X X X X yes
yes
no
yes
yes
yes
yes
yes
yes
no
no
yes
no
no
no
no
no
no
no
no
no
Note
1. ‘X’ is ‘don’t care’.
To read the addressed part of the time counter and alarm register, plus information from specified control/status flags,
the BCD digits in the DATA byte are organized as shown in Table 7.
The status of the CONTROL-nibble of the MODE-POINTER-WORD (C2, C1, C0) remains unchanged until re-written.
Table 7 Organization of the BCD digits in the DATA byte; note 1
MSB
UD
0
0
0
0
0
UPPER DIGIT
UC UB
0D
DD
0D
00
00
DATA
UA LD
DD
DD
DD
DD
ms
LOWER DIGIT
LC
D
D
D
D
NODA
LB
D
D
D
D
COMP
Note
1. ‘D’ is the data bit; ‘m’ = minutes; ‘s’ = seconds.
LSB
LA
D
D
D
D
POWF
ADDRESSED TO:
hours
minutes
days
months
control/status flags
1997 Mar 28
12

12 Page





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