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PCF8570P Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF8570P
Beschreibung 256 x 8-bit static low-voltage RAM with I2C-bus interface
Hersteller NXP Semiconductors
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Gesamt 20 Seiten
PCF8570P Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF8570
256 × 8-bit static low-voltage RAM
with I2C-bus interface
Product specification
Supersedes data of 1997 Sep 02
File under Integrated Circuits, IC12
1999 Jan 06






PCF8570P Datasheet, Funktion
Philips Semiconductors
256 × 8-bit static low-voltage RAM with
I2C-bus interface
Product specification
PCF8570
8.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
MBA605
Fig.5 System configuration.
8.4 Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
handbook, full pagewidth
START
condition
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
S
1
2
clock pulse for
acknowledgement
89
MBA606 - 1
Fig.6 Acknowledgement on the I2C-bus.
1999 Jan 06
6

6 Page









PCF8570P pdf, datenblatt
Philips Semiconductors
256 × 8-bit static low-voltage RAM with
I2C-bus interface
Product specification
PCF8570
13.2 Slave address
The PCF8570 has a fixed combination 1 0 1 0 as group 1, while group 2 is fully programmable (see Fig.12).
handbook, halfpage1 0 1 0 A2 A1 A0 R/W
group 1
group 2
MLB892
Fig.12 Slave address.
13.3 Power-saving mode
With the condition TEST = VDD or VDDR the PCF8570 goes into the power-saving mode and I2C-bus logic is reset.
handbook, full pagewidth
power saving
mode (1)
TEST = VDDR
operating mode
TEST
,,SCL
,,,,,,SDA
t SU (3)
,,,,,,,,tHD1(,,,,3)
VDD
IDD
power saving
mode (2)
TEST = VDD
VDD
VDDR
0V
,,,,,,,,,,,,tSU(3)
VDD
VDDR
0V
t HD2 (3)
VDD
VDDR
0V
VDD
VDDR
0V
IDD
IDDS
MLB932
(1) Power-saving mode without 5 V supply voltage.
(2) Power-saving mode with 5 V supply voltage.
(3) tSU and tHD1 4 µs and tHD2 50 µs.
Fig.13 Timing for power-saving mode.
1999 Jan 06
12

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