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PDF PCF8531 Data sheet ( Hoja de datos )
| Número de pieza | PCF8531 | |
| Descripción | 34 x 128 pixel matrix driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCF8531
34 × 128 pixel matrix driver
Product specification
Supersedes data of 1999 Aug 10
File under Integrated Circuits, IC12
2000 Feb 11
1 page  
Philips Semiconductors
34 × 128 pixel matrix driver
7 PINNING
SYMBOL
OSC
VLCDSENSE
VLCDOUT
VLCDIN
RES
VDD3
VDD2
VDD1
SDA
SDACK
SA0
ENR
T4
VSS2
VSS1
T3
T1
SCL
T2
R0
R2
R4
R6
R8
R10
R12
R14
R16
R18
R20
R22
R24
R26
R28
R30
R32
2000 Feb 11
PAD
1 to 14
15
16
17 to 23
24 to 30
31
32 to 34
35 to 42
43 to 49
50 and 51
52
53
54
55
56
57 to 63
64 to 70
71
72
73 and 74
75 to 77
78
79 to 86
87
88
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90
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102
103
DESCRIPTION
dummy pads
oscillator input; note 1
voltage multiplier regulation input (VLCD); note 2
voltage multiplier output (VLCD); note 3
LCD supply voltage (VLCD); note 2
external reset input (active LOW); note 4
supply voltage 3; note 5
supply voltage 2; note 5
supply voltage 1; note 5
serial data line input of the I2C-bus
serial data acknowledge output; note 6
dummy pad
I2C-bus slave address input; bit 0
enable internal Power-on reset input; note 7
test 4 input; note 8
ground 2; note 9
ground 1; note 9
test 3 input; note 8
test 1 input; note 8
serial clock line input of the I2C-bus
dummy pads
test 2 output; note 10
dummy pads
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
LCD row driver output
5
Product specification
PCF8531
5 Page 
Philips Semiconductors
34 × 128 pixel matrix driver
Product specification
PCF8531
8.17 Addressing
Data is written in bytes into the RAM matrix of the
PCF8531 as illustrated in Figs 5, 6 and 7. The display
RAM has a matrix of 34 × 128 bits. The columns are
addressed by the address pointer. The address ranges are
X 0 to X 127 (7FH) and Y 0 to Y 5 (5H). Addresses
outside of these ranges are not allowed. In vertical
addressing mode (V = 1), the Y address increments after
each byte (see Fig.6). After the last Y address (Y = 4),
Y wraps around to 0 and X increments to address the next
column. In horizontal addressing mode (V = 0), the
X address increments after each byte (see Fig.7). After the
last X address (X = 127), X wraps around to 0 and
Y increments to address the next row. After the very last
address (X = 127 and Y = 4), the address pointers wrap
around to address (X = 0 and Y = 0). It should be noted
that in bank 4 only the LSB (DB0) of the data will be written
into the RAM. The Y address 5 is reserved for icon data
and is not affected by the addressing mode; it should be
noted that in bank 5 only the 5th data bit (DB4) will be
written into the RAM.
handbook, full paLgSewBidth
MSB
LSB
MSB
LSB
MSB
icon data
0
X address
127
Fig.5 RAM format and addressing.
0
1
2
Y address
3
4
5
MGS469
handbook, full pagewidth
05
16
2
3
4
01
icon data
0
1
2
Y address
3
638 4
639 5
0
X address
127 MGS470
Fig.6 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
2000 Feb 11
11
11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet PCF8531.PDF ] | |
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