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PDF PCF85116-3 Data sheet ( Hoja de datos )
| Número de pieza | PCF85116-3 | |
| Descripción | 2048 x 8-bit CMOS EEPROM with I2C-bus interface | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCF85116-3
2048 × 8-bit CMOS EEPROM with
I2C-bus interface
Product specification
Supersedes data of 1997 Feb 24
File under Integrated Circuits, IC12
1997 Apr 02
1 page  
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
6 BLOCK DIAGRAM
Product specification
PCF85116-3
1997 Apr 02
5
5 Page 
Philips Semiconductors
2048 × 8-bit CMOS EEPROM with I2C-bus
interface
Product specification
PCF85116-3
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
SCL input (pin 6)
VIL LOW level input voltage
VIH HIGH level input voltage
ILI input leakage current
VI = VDD or VSS
fSCL clock input frequency
tSP pulse width of spikes suppressed by filter
CI input capacitance
VI = VSS
−0.8
0.7VDD
−
0
0
−
+0.3VDD
6.5
±1
400
100
7
WP input (pin 7)
VIL LOW level input voltage
VIH HIGH level input voltage
−0.8
0.9VDD
+0.1VDD
VDD + 0.8
Data retention time
tS data retention time
Tamb = 55 °C
20 −
Note
1. The bus capacitance ranges from 10 to 400 pF (Cb = total capacitance of one bus line in pF).
V
V
µA
kHz
ns
pF
V
V
years
11 I2C-BUS CHARACTERISTICS
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and
VIH with an input voltage swing from VSS to VDD.
SYMBOL
PARAMETER
STANDARD MODE
CONDITIONS
MIN.
MAX.
FAST MODE
UNIT
MIN.
MAX.
fSCL
tBUF
tHD;STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tr
tf
tSU; STO
clock frequency
time the bus must be free before
new transmission can start
START condition hold time after
which first clock pulse is generated
LOW level clock period
HIGH level clock period
set-up time for START condition
data hold time
for CBUS compatible masters
for I2C-bus devices
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
repeated start
note 1
0
4.7
4.0
4.7
4.0
4.7
5
0
250
−
−
4.0
100 0
− 1.3
− 0.6
− 1.3
− 0.6
− 0.6
400 kHz
− µs
− µs
− µs
− µs
− µs
−
−
−
1 000
300
−
−−
0−
100 −
20 + 0.1Cb(2) 300
20 + 0.1Cb(2) 300
0.6 −
µs
ns
ns
ns
ns
µs
Notes
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
internally provided by a transmitter.
2. Cb = total capacitance of one bus line in pF.
1997 Apr 02
11
11 Page | ||
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| PDF Descargar | [ Datasheet PCF85116-3.PDF ] | |
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