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PCF85103C-2P Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF85103C-2P
Beschreibung 256 x 8-bit CMOS EEPROMs with I2C-bus interface
Hersteller NXP Semiconductors
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Gesamt 20 Seiten
PCF85103C-2P Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF85102C-2; PCF85103C-2
256 × 8-bit CMOS EEPROMs with
I2C-bus interface
Product specification
File under Integrated Circuits, IC12
2000 Feb 15






PCF85103C-2P Datasheet, Funktion
Philips Semiconductors
256 × 8-bit CMOS EEPROMs with
I2C-bus interface
Product specification
PCF85102C-2; PCF85103C-2
7 PINNING
PCF8510xC-2 has standard industrial pinning which will be compatible for most applications.
7.1 Pin description PCF85102C-2
SYMBOL PIN
DESCRIPTION
A0 1 address input 0
A1 2 address input 1
A2 3 address input 2
VSS
SDA
SCL
4 negative supply voltage
5 serial data input/output (I2C-bus)
6 serial clock input (I2C-bus)
n.c. 7 not connected
VDD 8 positive supply voltage
handbook, halfpage
A0 1
8 VDD
A1 2
7 n.c.
PCF85102C-2
A2 3
6 SCL
VSS 4
5 SDA
MGL968
Fig.2 Pin configuration PCF85102C-2.
7.2 Pin description PCF85103C-2
SYMBOL PIN
DESCRIPTION
WP 1 address input 0
A1 2 address input 1
A2 3 address input 2
VSS
SDA
SCL
4 negative supply voltage
5 serial data input/output (I2C-bus)
6 serial clock input (I2C-bus)
n.c. 7 not connected
VDD 8 positive supply voltage
handbook, halfpage
WP 1
8 VDD
A1 2
7 n.c.
PCF85103C-2
A2 3
6 SCL
VSS 4
5 SDA
MGL969
Fig.3 Pin configuration PCF85103C-2.
2000 Feb 15
6

6 Page









PCF85103C-2P pdf, datenblatt
Philips Semiconductors
256 × 8-bit CMOS EEPROMs with
I2C-bus interface
Product specification
PCF85102C-2; PCF85103C-2
11 I2C-BUS CHARACTERISTICS
All timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Fig.10; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
fSCL clock frequency
0 100 kHz
tBUF bus free time between a STOP and START
condition
4.7
µs
tHD;STA
START condition hold time after which first clock
pulse is generated
4.0
µs
tLOW
LOW-level clock period
4.7
µs
tHIGH
HIGH-level clock period
4.0
µs
tSU;STA
set-up time for START condition
repeated start 4.7
µs
tHD;DAT
data hold time
for bus compatible masters
5 − µs
for bus devices
note 1
0 ns
tSU;DAT
data set-up time
250
ns
tr SDA and SCL rise time
1 µs
tf SDA and SCL fall time
300 ns
tSU;STO
set-up time for STOP condition
4.0
µs
Note
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
internally provided by a transmitter.
12 WRITE CYCLE LIMITS
Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either VSS or VDD.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
E/W cycle timing
tE/W E/W cycle time
Endurance
NE/W
E/W cycle per byte
internal oscillator
Tamb = 40 to +85 °C
Tamb = 22 °C
7
100000
1000000
UNIT
ms
cycles
cycles
2000 Feb 15
12

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