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PDF PCF85103C-2 Data sheet ( Hoja de datos )
| Número de pieza | PCF85103C-2 | |
| Descripción | 256 x 8-bit CMOS EEPROM with I2C-bus interface | |
| Fabricantes | NXP Semiconductors | |
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PCF85103C-2
256 × 8-bit CMOS EEPROM with I2C-bus interface
Rev. 02 — 09 May 2002
Product data
1. Description
The PCF85103C-2 is a floating gate Electrically Erasable Programmable Read Only
Memory (EEPROM) with 2 kbits (256 × 8-bit) non-volatile storage. By using an
internal redundant storage code, it is fault tolerant to single bit errors. This feature
dramatically increases the reliability compared to conventional EEPROMs. Power
consumption is low due to the full CMOS technology used. The programming voltage
is generated on-chip, using a voltage multiplier.
Data bytes are received and transmitted via the serial I2C-bus. Up to eight
PCF85103C-2 devices may be connected to the I2C-bus. Chip select is accomplished
by three address inputs (A0, A1 and A2).
The PCF85103C-2 is identical to PCF85102C-2 except for the fixed I2C address,
allowing up to eight PCF85102C-2 and eight PCF85103C-2 on the same I2C-bus.
2. Features
s Low power CMOS:
x 2.0 mA maximum operating current
x maximum standby current 10 µA (at 6.0 V), typical 4 µA
s Non-volatile storage of 2 kbits organized as 256 × 8-bit
s Single supply with full operation down to 2.5 V
s On-chip voltage multiplier
s Serial input/output I2C-bus
s Write operations:
x byte write mode
x 8-byte page write mode (minimizes total write time per byte)
s Read operations:
x sequential read
x random read
s Internal timer for writing (no external components)
s Internal power-on reset
s 0 to 100 kHz clock frequency
s High reliability by using a redundant storage code
s Endurance: 1,000,000 Erase/Write (E/W) cycles at Tamb = 22 °C
s 10 years non-volatile data retention time
s Pin compatible to: PCF8570, PCF8571, PCF8572, PCA8581, PCF8582, and
PCF85102
1 page  
Philips Semiconductors
PCF85103C-2
256 × 8-bit CMOS EEPROM with I2C-bus interface
I2C-BUS
PCF85103C-2
DEVICE 1
256-BYTE PAGE
A2 A1 A0
0 00
PCF85103C-2
DEVICE 2
256-BYTE PAGE
0 01
PCF85103C-2
DEVICE 3
256-BYTE PAGE
0 10
PCF85103C-2
DEVICE 4
256-BYTE PAGE
0 11
PCF85103C-2
DEVICE 5
256-BYTE PAGE
1 00
PCF85103C-2
DEVICE 6
256-BYTE PAGE
1 01
PCF85103C-2
DEVICE 7
256-BYTE PAGE
1 10
Fig 3. Device addressing.
PCF85103C-2
DEVICE 8
256-BYTE PAGE
1 11
002aaa252
9397 750 09646
Product data
Rev. 02 — 09 May 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5 of 20
5 Page 
Philips Semiconductors
PCF85103C-2
256 × 8-bit CMOS EEPROM with I2C-bus interface
11. I2C-bus characteristics
Table 7: I2C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Figure 9.
Symbol
Parameter
Conditions
Min Max Unit
fSCL clock frequency
tBUF bus free time between a STOP and
START condition
0 100 kHz
4.7 −
µs
tHD;STA
START condition hold time after
which first clock pulse is generated
4.0 −
µs
tLOW
tHIGH
tSU;STA
LOW level clock period
HIGH level clock period
set-up time for START condition
repeated start
4.7 −
4.0 −
4.7 −
µs
µs
µs
tHD;DAT
data hold time
for bus compatible masters
5 − µs
for bus devices
[1] 0 − ns
tSU;DAT
tr
tf
tSU;STO
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
250 −
ns
− 1 µs
− 300 ns
4.0 −
µs
[1] The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
SDA
t BUF
t LOW
SCL P
S
t HD;STA
t r t HD;DAT
P = STOP condition; S = START condition.
Fig 9. Timing requirements for the I2C-bus.
tf
t HIGH
t SU;DAT
t HD;STA
S
t SU;STA
MBA705
P
t SU;STO
9397 750 09646
Product data
Rev. 02 — 09 May 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
11 of 20
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