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PCF84C41AT Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF84C41AT
Beschreibung Telecom microcontrollers
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 20 Seiten
PCF84C41AT Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF84C21A; PCF84C41A;
PCF84C81A
Telecom microcontrollers
Product specification
Supersedes data of 1995 Jul 14
File under Integrated Circuits, IC14
1996 Nov 20






PCF84C41AT Datasheet, Funktion
Philips Semiconductors
Telecom microcontrollers
Product specification
PCF84C21A; PCF84C41A;
PCF84C81A
8 ROM MASK OPTIONS
ROM CODE
Program/data
Port Output
P0.0 to P0.7
P1.0 to P1.7
P2.0 to P2.2
SDA/P2.3
Port State after reset
P0.0 to P0.7
P1.0 to P1.7
P2.0 to P2.2
SDA/P2.3
Oscillator
Transconductance
OPTION
Any mix of instructions and data up to ROM size of
2 kbytes for the PCF84C21A, 4 kbytes for the
PCF84C41A and 8 kbytes for the PCF84C81A.
standard
standard
standard
open-drain
open-drain
open-drain
open-drain
push-pull
push-pull
push-pull
set
reset
set
reset
set
reset
set
LOW (gmL)
MEDIUM (gmM) HIGH (gmH)
9 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices. See “Data Handbook IC14, Section: Handling MOS devices”.
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
VI
II
IO
IO
Ptot
PO
IDD
ISS
Tstg
Tj
PARAMETER
supply voltage
all input voltages
DC input current
DC output current except Port 1 output LOW
DC output current, Port 1 output LOW
total power dissipation
power dissipation per output
supply current
ground supply current
storage temperature range
operating junction temperature
MIN.
0.5
0.5
10
10
10
50
100
55
MAX.
+7
VDD + 0.5
+10
+10
+20
125
30
+50
+50
+150
90
UNIT
V
V
mA
mA
mA
mW
mW
mA
mA
°C
°C
1996 Nov 20
6

6 Page









PCF84C41AT pdf, datenblatt
Philips Semiconductors
Telecom microcontrollers
Product specification
PCF84C21A; PCF84C41A;
PCF84C81A
SCLK
SDA/P2.3
t HIGH
t LOW
t BUF
t HD;STA
t RC
t RD
t HD;DAT t SU;DAT
0.7 V DD
0.3 VDD
0.7 V DD
0.3 VDD
t FC t FD
t SU;STO
MBB568
Fig.15 Slave SCLK receiver SDA/P2.3 timing (SCLK and SDA/P2.3 are inputs).
SCLK
SDA/P2.3
t HD;STA
t LOW
t HIGH
t FC
t HD;DAT
t SU;DAT
0.9 VDD
VOLmax
t FD
acknowledge bit
0.9 V DD
VOLmax
t HD;DAT
t HD;DAT
t SU;STO
t SU;DAT
MBB569
Fig.16 Master SCLK and transmitter SDA/P2,3 timing (SCLK and SDA/P2.3 are outputs).
1996 Nov 20
12

12 Page





SeitenGesamt 20 Seiten
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