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PCF5079 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF5079
Beschreibung Dual-band power amplifier controller for GSM/ PCN and DCS
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 28 Seiten
PCF5079 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF5079
Dual-band power amplifier
controller for GSM, PCN and DCS
Product specification
File under Integrated Circuits, IC17
2001 Nov 21






PCF5079 Datasheet, Funktion
Philips Semiconductors
Dual-band power amplifier controller for
GSM, PCN and DCS
Product specification
PCF5079
7 FUNCTIONAL DESCRIPTION
7.1 General
The PCF5079 contains an integrated amplifier for the
detected RF voltage from the sensor, an integrator and an
active filter to build up a PA control loop for cellular
systems with a small number of passive components
suitable for dual-band applications. The active band can
be selected by means of the dedicated input BS.
The sensor amplifier can amplify signals from an
RF power detector in a range of less than 20 to +15 dBm.
This can comply to the PA output power range of
GSM900/1800/1900 systems when, for example, a
directional coupler with 20 dB attenuation is used for
GSM900 and a directional coupler with 18 dB attenuation
is used for GSM1800.
The external Schottky diodes for power detection (sensor)
are biased by an integrated current source of 30 µA.
Variations of the forward voltage with temperature have no
influence on the measured signal because they are
cancelled by the switched capacitor amplifier OP1.
An external DAC with at least 10-bit resolution (for
example, AUXDAC3 of baseband interface family
PCF5073x) is necessary to control the loop.
An integrated active filter smooths the voltage steps of the
DAC during ramp-up and ramp-down.
The operation principle is the same, independently of the
selected standard. The DAC signal and the sensor signal
are added by amplifier OP1. The voltage difference of both
signals is integrated by operational amplifier OP4
dedicated to the selected standard, which delivers the
PA control voltage on an external capacitance, CINT1 or
or CINT2, between pins VINT(N) and VCD or VCG,
respectively. The shape of the rising and falling power
burst edges can be determined by means of the DAC
voltage.
7.2 Power-up mode
The device includes a power-up input (pin PU) to switch
the IC on during time slots that are used in TDMA systems,
and to switch the IC off during the unused slots to reduce
current consumption.
7.3 OP4 (integrator)
The operational amplifier OP4 (integrator) consists of a
shared input stage, OP4IN and a dedicated output driver
for each standard, OP4G and OP4D. Depending on the
status of input BS, one driver is active and the other is kept
in power-down mode during active time slots.
7.4 Start-up and initial conditions
The PCF5079 is designed to operate in bursts, as required
in TDMA systems. Referring to Fig.4, for each time slot to
be transmitted the PCF5079 must be enabled by setting
signal PU to logic 1. Once pin PU is active, BS is taken
into account to allow correct initialisation of switches S1,
SFD, SFG, S3, S4 and S5, and of the configuration signals
PUG and PUD.
The feedback switch across the unused driver is kept open
and the output voltage from the unused driver is tied to VSS
to maintain the off state of the unused PA.
When pin PU is set to logic 1, at least 5 µs after VDD has
reached its final value, switches S1, the appropriate switch
SFD or SFG and S3 are closed, and switches S4 and S5
are opened. Because switch S1 is closed, the forward
voltage of Schottky diodes D1 and D2 is sampled on
capacitors C1 and C2 respectively.
Moreover, the control voltage on pin VCD or VCG is
initially forced to be at the pre-bias voltage because the
appropriate switch SFD or SFG and S3 are closed, and S4
is opened.
After a fixed time, defined on-chip, switch S1 is opened
and the circuit is ready.
Once switch S1 is open, a ramp signal applied at
pin VDAC (at least 20 µs after the transition of pin PU from
logic 0 to logic 1) with an amplitude of at least 70 mV, from
CODESTART to CODEKICK, determines the opening of
switch S3 and closing of switch S4 on the home voltage,
with a delay of 3 µs maximum with respect to the ramp.
After switch S3 opens (in a fixed amount of time), the
control voltage on pin VCD or pin VCG rises to the home
position to bias the PA to the beginning of the active range
of its control curve. During this time (typically 2 µs), the
appropriate switch SFD or SFG remains closed. When the
appropriate switch SFD or SFG is opened, switch S5 is
closed, allowing the transfer of any signal coming from
amplifier OP1. After this preset, the control voltage is free
to increase according to the control loop if the RF input is
enabled (see Fig.12).
For higher DAC ramp steps, the delay of switch S3
opening (S4 closing) is reduced while the delay between
switch SFD (SFG) opening with respect to S3 opening
(S4 closing) remains unchanged.
2001 Nov 21
6

6 Page









PCF5079 pdf, datenblatt
Philips Semiconductors
Dual-band power amplifier controller for
GSM, PCN and DCS
Product specification
PCF5079
SYMBOL
PARAMETER
CONDITION
MIN. TYP. MAX. UNIT
ILH
HIGH-level input leakage current
VIH = 5.0 V
CI input capacitance
5
+5 µA
10 pF
Sensor inputs and bias current source (pins VS1 and VS2)
VVS2
VVS1
Ibias1,
Ibias2
input voltage
input voltage
bias current source for detector
diodes D1 and D2
TCIbias1, temperature coefficient of
TCIbias2 Ibias1 and Ibias2
VI = 0 V; Tamb = 25 °C; see Fig.6
VDD = 2.5 V
VDD = 5.0 V
3
3
17
21
VDD V
VDD V
28 39
33 45
0.07
µA
µA
mA/K
Internal home position voltage
Vhome
internal home position voltage
TCVhome temperature coefficient for Vhome
Tamb = 25 °C
0.550 0.600 0.650 V
− −2.1 mV/K
Note
1. A resistive load on pins VCD or VCG to ground (VSS) does not result in additional current consumption.
35
handbook, halfpage
Ibias
(µA)
33
MGT332
31
29
27
2.5 3 3.5 4 4.5 5
VDD (V)
Fig.6 Typical value of Ibias as a function of
VDD at Tamb = 25 °C.
2001 Nov 21
12

12 Page





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