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PCF50732H Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF50732H
Beschreibung Baseband and audio interface for GSM
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCF50732H Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF50732
Baseband and audio interface for
GSM
Objective specification
File under Integrated Circuits, IC17
1999 May 03






PCF50732H Datasheet, Funktion
Philips Semiconductors
Baseband and audio interface for GSM
Objective specification
PCF50732
7 PINNING
SYMBOL
NR. TYPE(1)
ADO
ADI
AFS
1 O/TS
2I
3I
ACLK
RESET
MCLK
4
5
6
I
I
I
VDDD
VSSD
CCLK
CEN
CDI
CDO
AUXST
7P
8G
9I
10 I
11 I
12 O/TS
13 I
AMPCTRL
BIOCLK
BIEN
BDIO
BOEN
TXON
RXON
IP
IN
14
15
16
17
18
19
20
21
22
O
O/TS
O
I/O
O
I
I
I/O
I/O
QP 23 I/O
QN 24 I/O
VDDA(bb)
VSSA(bb)
AUXADC1
AUXADC2
AUXADC3
AUXADC4
AUXDAC1
AUXDAC2
25
26
27
28
29
30
31
32
P
G
I
I
I
I
O
O
PIN
ACTIVE
LEVEL
LOW
LOW
HIGH
LOW
LOW
HIGH
HIGH
ACTIVE
EDGE
IDD
DESCRIPTION
1.5 mA audio digital interface PCM data output to DSP
− − audio digital interface PCM data input from DSP
rising
audio digital interface PCM frame synchronization signal
from DSP
rising
audio digital interface PCM clock signal from DSP
rising
asynchronous reset input
low-swing master clock input; fclk = 13 MHz; integrated
capacitive coupling
− − digital power supply
− − digital ground
falling
control bus clock input from DSP
control bus data enable from DSP
− − control bus data input from DSP
1.5 mA control bus data output to DSP
− − status control signal for activation of AUXDAC1,
AUXDAC2 and MCLK input
1.5 mA general purpose output pin
3 mA baseband interface data clock
1.5 mA baseband transmit interface data enable signal
1.5 mA baseband interface data I/O from/to DSP
1.5 mA baseband receive interface data enable signal
− − baseband transmit path activation signal
− − baseband receive path activation signal
− − (I) baseband differential positive input/output to IF circuit
− − (I) baseband differential negative input/output to
IF circuit
− − (Q) baseband differential positive input/output to
IF circuit
− − (Q) baseband differential negative input/output to
IF circuit
− − baseband power supply (analog)
− − baseband ground (analog)
− − auxiliary ADC input 1 for battery voltage measurement
− − auxiliary ADC input 2
− − auxiliary ADC input 3
− − auxiliary ADC input 4
− − auxiliary DAC output for AGC; max. load 50 pF // 2 k
− − auxiliary DAC output for AFC; max. load 50 pF // 10 k
1999 May 03
6

6 Page









PCF50732H pdf, datenblatt
Philips Semiconductors
Baseband and audio interface for GSM
Objective specification
PCF50732
9.3.2.2 Power ramping controller
The PCF50732 fully supports all multislot modes which do
not require full duplex operation or more than two
consecutive transmit bursts. In this specification double
burst mode is used for all supported multislot modes while
single burst mode supports the normal GSM modes.
The power ramping controller drives the power amplifier
output envelope.
In each transmit (TX) burst one ramp-up and one
ramp-down will be carried out. In multislot mode one
intermediate ramp will be carried out in addition to ramp-up
and ramp-down. Each ramp consists of 16 discrete step
values that are sent to the DAC3. Each step’s duration is
2 quarterbits which translates into 8-bit long ramps.
The DAC3 output is in 3-state whenever it is powered
down. The ramping step values are stored in a 64 × 10-bit
RAM as shown in Table 2.
In order to initialize AUXDAC3 it is necessary to write into
the RAM all 32 (or 48 in multislot mode) DAC3 output
values. Filling the RAM is normally done by writing a
logic 0 to the address sub-register of the Burst control
register, after which 32 or 48 values, depending on
multislot mode, can be written into the data sub-register of
the Burst control register. Writing to the DAC3 RAM is only
possible when the DAC3 is powered off.
Total number of CSI-accesses is therefore 33 for a normal
burst and 49 for a double burst.
An autoincrement feature will store these data into the
correct RAM positions.
The value after power-up of DAC3 will always be equal to
the value of RAM location 47.
AUXDAC3 timing is controlled by the Burst control
register. This contains the following sub-registers:
The RU register containing the delay in number of
quarterbit cycles from the assertion of TXON to the start
of the power-up ramping; default value is 0
The RM register containing the delay in number of
quarterbit cycles from the assertion of TXON to the start
of the intermediate power ramp; default value is 0. RM
is only used in case of multislot mode
The RD register containing the delay in number of
quarterbit cycles from the assertion of TXON to the start
of the power-down ramping; default value is 0
DAC3 burst RAM address register
DAC3 burst RAM data register
Single/double burst mode register: normal mode or
multislot mode selection flag.
After TXON goes HIGH and a time equal to RU quarterbit
periods has elapsed, power ramp-up is done.
After a time period equal to RD quarterbits has elapsed
power ramp-down is initiated.
The AUXDAC3 output is also shown in Fig.4.
Values for RU (ramp-up) and RD (ramp-down) can be set
in the Burst control register of the control serial interface.
RD must be greater than RU + 32. RU and RD range
from 0 to 4000 QB (quarterbit). The register offers the
possibility to enter codes up to 4095.
The GMSK modulator is active for a period of 2 clock
cycles after the ramp-down or for the length of the TXON
burst, whichever is longer.
Multislot (high speed switched data mode) can be selected
by setting the appropriate bit in the Burst control register.
In multislot mode an intermediate ramping step is done.
This intermediate step is started after a time period equal
to RM quarterbits has elapsed. A value for RM
(intermediate ramp) is also set using the Burst control
register. The following conditions must be true:
RU + 32 < RM and RM + 32 < RD.
Table 2 AUXDAC3 RAM contents
RAM ADDRESS
0 to 15
16 to 31
32 to 47
48 to 64
DATA
ramp-up data
intermediate ramp data
ramp-down data
not used
Table 3 Power ramping timing characteristics
SYMBOL
VALUE
COMMENTS(1)
t0
tru
tim
trd
trup, trim, trdo
12t1
RU register
RM register
RD register
32t0
one quarterbit (QB)
0 to 4000 QB
RU + 32 to 4000 QB
RM + 32 to 4000 QB
8 bits; 32 QB
Note
1. QB: Quarterbit, usually referred to the time needed for
one quarter of a GSM baseband bit, i.e. a frequency of
112 × 13 MHz.
1999 May 03
12

12 Page





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