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PCF5001 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF5001
Beschreibung POCSAG Paging Decoder
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCF5001 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF5001
POCSAG Paging Decoder
Product specification
Supersedes data of 1995 Apr 27
File under Integrated Circuits, IC17
1997 Mar 04






PCF5001 Datasheet, Funktion
Philips Semiconductors
POCSAG Paging Decoder
Product specification
PCF5001
6 PINNING
SYMBOL
Vref
CN
CP
VDD
DI
BS
PD
PS
X1
X2
TS
AH
OL
PIN
PCF5001T PCF5001H
(SOT136-1) (SOT358-1)
DESCRIPTION
1 13 Microcontroller interface reference voltage input/output. The LOW level of
pins FL, DS, DO, OR, BL, AI, ON, SK, SR and IE is related to the voltage
on Vref. May be driven from an external negative voltage source or must
be connected to VSS, if pins CN and CP are left open-circuit. When the
on-chip voltage converter is used, this pin provides a doubled negative
output voltage.
2 14 Voltage converter external shunt capacitance, negative side. Connect the
negative side of the shunt capacitor to this pin, if the on-chip voltage
converter function is used.
3 15 Voltage converter external shunt capacitor, positive side. Connect the
positive side of the shunt capacitor to this pin, if the on-chip voltage
converter function is used.
4 16 Main positive power supply. This pin is common to all supply voltages and
is referred to as 0 V (common).
5 17 Serial data input (POCSAG code). The serial data signal train applied to
this pin is processed by the decoder. Pulled LOW by an on-chip pull-down
when the receiver is disabled (RE = LOW).
6 18 Battery-low indication input. The decoder samples this input during
synchronization scan, when it is in ON or SILENT status and the receiver
is enabled (RE = HIGH). A battery-low condition is assumed, if the
decoder detects four consecutive samples HIGH. An audible battery-low
indication is made by the decoder, when operating in ON status. Normally
LOW by the operation of an on-chip pull-down.
7 19 EEPROM programming data input and output. Normally HIGH by the
operation of an on-chip pull-up. During programming of the on-chip
EEPROM, PD is a bidirectional data and control signal.
8 22 EEPROM programming strobe input. Normally LOW by the operation of
an on-chip pull-down. During programming of the on-chip EEPROM, PS is
a unidirectional control input.
9 23 Crystal oscillator input. Connect a 32768 Hz or 76800 Hz crystal and a
biasing resistor between this pin and X2. In addition, provide a load
capacitance to VDD, which may also be used for frequency tuning.
10 24 Crystal oscillator output. Return connection for the external crystal and
resistor at X1.
11 25 Scan test mode enable input. Always LOW by operation of an on-chip
pull-down.
12 26 Alert HIGH-level output. This output can directly drive an external bipolar
transistor to control HIGH-level alerting in conjunction with AL, by means
of an alerter or beeper.
13 27 LED indication output. This output can directly drive an external bipolar
transistor to control the visual alert function by means of an LED. It may
also be used for visual indication of received call data during call
reception.
1997 Mar 04
6

6 Page









PCF5001 pdf, datenblatt
Philips Semiconductors
POCSAG Paging Decoder
Product specification
PCF5001
IE
ON
SK
INTERNAL
STATUS
t STP
t STD
t STD
t IEH
t STH
MCD457 - 1
Fig.6 Status change in display pager mode.
IE
SR
t STP t STH
t SPD
t IEH
t STH
MCD458
Fig.7 Status interrogation in display pager mode.
7.4 Decoding of the POCSAG data stream
The POCSAG coded input data stream is first noise filtered
by a digital filter. From the filtered data a sampling clock
synchronous to the data rate is derived. The PCF5001
supports 512 bits/s and 1200 bits/s data rates. This results
in a 512 Hz or 1200 Hz sampling clock frequency,
respectively. Synchronization on the POCSAG code
structure is performed using the improved Philips
ACCESS® algorithm, which employs a state machine with
six internal states.
A data rate of 2400 bits/s is possible if an external clock
generator of 153.6 kHz is connected to X1. The minimum
supply voltage is then 1.8 V.
The receiver enable output is activated a period equal to
tRXON before the input data is actually needed. The
decoder has first to achieve bit and word synchronization
before it can receive calls. The algorithm searches first for
the preamble and then for synchronization codeword
patterns.
1997 Mar 04
12

12 Page





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