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PDF PCF2116AHZ Data sheet ( Hoja de datos )
| Número de pieza | PCF2116AHZ | |
| Descripción | LCD controller/drivers | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCF2116 family
LCD controller/drivers
Product specification
Supersedes data of 1996 Oct 25
File under Integrated Circuits, IC12
1997 Apr 07
1 page  
Philips Semiconductors
LCD controller/drivers
6 PINNING
SYMBOL
R31
n.c.
R32
C60 to C30
n.c.
C29 to C2
n.c.
C1
R24 to R17
R8 to R1
n.c.
DB7
SCL
DB6
SDA
DB5
V0
VLCD1
DB4
VLCD2
DB3
VLCD3
DB2
n.c.
OSC
DB1
VDD2
DB0
VDD1
SA0
E
VSS1
R/W
T1
VSS2
RS
n.c.
R9 to R16
R25 to R30
LQFP128
1
2 and 3
4
5 to 35
36 and 37
38 to 65
66 and 67
68
69 to 76
77 to 84
85 and 86
87
88
89
90
91
92
93
94
95
96
97
98
99 to 101
102
103
104
105
106
107
108
109
110
111
112
113
114
115 to 122
123 to 128
FFC PAD
27
−
28
29 to 59
−
60 to 87
−
88
89 to 96
97 to 104
−
105
106
107
108
109
110
111
112
113
114
115
116
−
1
2
3
4
5
6
7
8
9
10
11
12
−
13 to 20
21 to 26
1997 Apr 07
Product specification
PCF2116 family
TYPE
O
−
O
O
−
O
−
O
O
O
−
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
−
I
I/O
P
I/O
P
I
I
P
I
I
P
I
−
O
O
DESCRIPTION
LCD row driver output
not connected
LCD row driver output
LCD column driver outputs 60 to 30
not connected
LCD column driver outputs 29 to 2
not connected
LCD column driver output 1
LCD row driver outputs
LCD row driver outputs
not connected
1 bit of 8-bit bidirectional data bus
I2C-bus serial clock input
1 bit of 8-bit bidirectional data bus
I2C-bus serial data input/output
1 bit of 8-bit bidirectional data bus
control input for VLCD
LCD supply voltage input/output 1
1 bit of 8-bit bidirectional data bus
LCD supply voltage input/output 2
1 bit of 8-bit bidirectional data bus
LCD supply voltage input/output 3
1 bit of 8-bit bidirectional data bus
not connected
oscillator/external clock input
1 bit of 8-bit bidirectional data bus
supply voltage 2
1 bit of 8-bit bidirectional data bus
supply voltage 1
I2C-bus address pin
data bus clock input (parallel control)
ground (logic) 1
read/write input (parallel control)
test pad (connect to VSS)
ground (logic) 2
register select input (parallel control)
not connected
LCD row driver outputs
LCD row driver outputs
5
5 Page 
Philips Semiconductors
LCD controller/drivers
Product specification
PCF2116 family
8.10 Address Counter (AC)
The Address Counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
instructions ‘Set CGRAM address’ and
‘Set DDRAM address’. After a read/write operation the
Address Counter is automatically incremented or
decremented by 1.The Address Counter contents are
output to the bus (DB0 to DB6) when RS = logic 0 and
R/W = logic 1.
8.11 Display data RAM (DDRAM)
The display data RAM stores up to 80 characters of
display data represented by 8-bit character codes.
RAM locations not used for storing display data can be
used as general purpose RAM. The basic
DDRAM-to-display mapping scheme is shown in Fig.5.
With no display shift the characters represented by the
codes in the first 12 or 24 RAM locations starting at
address 00 in line 1 are displayed. Subsequent lines
display data starting at addresses 20, 40, or 60 Hex.
Figs 6 and 7 show the DDRAM-to-display mapping
principle when the display is shifted.
The address range for a 1-line display is 00 to 4F; for a
2-line display from 00 to 27 (line 1) and 40 to 67 (line 2);
for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and
60 to 73 for lines 1, 2, 3 and 4 respectively.
For 2 and 4-line displays the end address of one line and
the start address of the next line are not consecutive.
When the display is shifted each line wraps around
independently of the others (Figs 6 and 7).
When data is written into the DDRAM wrap-around occurs
from 4F to 00 in 1-line mode and from 27 to 40 and
67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60
and 73 to 00 in 4-line mode.
8.13 Character generator RAM (CGRAM)
Up to 16 user-defined characters may be stored in the
character generator RAM. The CGROM and CGRAM use
a common address space, of which the first column is
reserved for the CGRAM (see Fig.8). Figure 11 shows the
addressing principle for the CGRAM.
8.14 Cursor control circuit
The cursor control circuit generates the cursor (underline
and/or character blink as shown in Fig.12) at the DDRAM
address contained in the Address Counter. When the
Address Counter contains the CGRAM address the cursor
will be inhibited.
8.15 Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
8.16 LCD row and column drivers
The PCF2116 contains 32 row and 60 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display, in accordance with the data to be
displayed. The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 13 and 14 show typical waveforms.
In 1-line mode (1 : 16) the row outputs are driven in pairs:
R1/R17, R2/R18 for example. This allows the output pairs
to be connected in parallel, providing greater drive
capability.
Unused outputs should be left unconnected.
8.12 Character generator ROM (CGROM)
The character generator ROM generates 240 character
patterns in 5 × 8 dot format from 8-bit character codes.
Figures 8 to 10 show the character sets currently
available.
1997 Apr 07
11
11 Page | ||
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| PDF Descargar | [ Datasheet PCF2116AHZ.PDF ] | |
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