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PCF2104C Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF2104C
Beschreibung LCD controller/driver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 56 Seiten
PCF2104C Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF2104x
LCD controller/driver
Product specification
Supersedes data of 1997 Apr 01
File under Integrated Circuits, IC12
1997 Dec 16






PCF2104C Datasheet, Funktion
Philips Semiconductors
LCD controller/driver
Product specification
PCF2104x
7.8 OSC: oscillator
When the on-chip oscillator is used, this pin must be
connected to VDD. An external clock signal, if used, is input
at this pin.
8.2 Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pin OSC must be connected to VDD.
7.9 SCL: serial clock line
Input for the I2C-bus clock signal.
7.10 SDA: serial data line
Input/output for the I2C-bus data line.
7.11 SA0: address pin
The hardware sub-address line is used to program the
device sub-address for 2 different PCF2104xs on the
same I2C-bus.
7.12 T1: test pad
Must be connected to VSS. Not user accessible.
8 FUNCTIONAL DESCRIPTION (see Fig.1)
8.1 LCD bias voltage generator
The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system power consumption. The optimum levels depend
on the multiplex rate and are selected automatically when
the number of lines in the display is defined.
The optimum value of VOP depends on the multiplex rate,
the LCD threshold voltage (Vth) and the number of bias
levels. The relationships are given in Table 1.
Using a 5-level bias scheme for 1 : 16 MUX rate allows
VOP < 5 V for most LCD liquids. The effect on the display
contrast is negligible.
Table 1 Optimum values for VOP
MUX
RATE
NUMBER
OF BIAS
LEVELS
VOP/Vth
DISCRIMINATION
Von/Voff
1 : 16
1 : 32
5
6
3.67
5.19
1.277
1.196
8.3 External clock
If an external clock is to be used, it must be input at
pin OSC. The resulting display frame frequency is given by
fframe = 12304fosc. A clock signal must always be present,
otherwise the LCD may be frozen in a DC state.
8.4 Power-on reset
The Power-on reset block initializes the chip after
power-on or power failure.
8.5 Registers
The PCF2104x has two 8-bit registers, an instruction
register (IR) and a data register (DR). The register select
signal (RS) determines which register will be accessed.
The instruction register stores instruction codes such as
display clear and cursor shift, and address information for
the Display Data RAM (DDRAM) and Character Generator
RAM (CGRAM). The instruction register can be written to,
but not read from, by the system controller.
The data register temporarily stores data to be read from
the DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM (corresponding to the address in the
Address Counter) is written to the data register prior to
being read by the ‘Read data’ instruction.
8.6 Busy Flag
The Busy Flag indicates the free/busy status of the
PCF2104x. Logic 1 indicates that the chip is busy and
further instructions will not be accepted. The Busy Flag is
output at pin DB7 when RS = logic 0 and R/W = logic 1.
Instructions should only be written after checking that the
Busy Flag is at logic 0 or waiting for the required number
of clock cycles.
1997 Dec 16
6

6 Page









PCF2104C pdf, datenblatt
Philips Semiconductors
LCD controller/driver
Product specification
PCF2104x
handbook, full pagewiduthpper
lower 4 bits
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
xxxx
0000
CG
RAM 1
xxxx 0001 2
xxxx 0010 3
xxxx 0011 4
xxxx 0100 5
xxxx 0101 6
xxxx 0110 7
xxxx 0111 8
xxxx 1000 9
xxxx 1001 10
xxxx 1010 11
xxxx 1011 12
xxxx 1100 13
xxxx 1101 14
xxxx 1110 15
xxxx 1111 16
Fig.7 Character set ‘N’ in CGROM; PCF2104N.
MGM134
1997 Dec 16
12

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