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PCF2103EU Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF2103EU
Beschreibung LCD controllers/drivers
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCF2103EU Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF2103 family
LCD controllers/drivers
Product specification
File under Integrated Circuits, IC12
1998 May 11






PCF2103EU Datasheet, Funktion
Philips Semiconductors
LCD controllers/drivers
Product specification
PCF2103 family
Table 1 Pin functions; note 1
NAME
FUNCTION
DESCRIPTION
RS register select RS selects the register to be accessed for read and write; there is an internal pull-up
on this pin
RS = 0 selects the instruction register for write and the busy flag and address
counter for read
RS = 1 selects the data register for both read and write
R/W
read/write
R/W selects either the read (R/W = 1) or write (R/W = 0) operation; there is an
internal pull-up on this pin
E data bus clock pin E is set HIGH to signal the start of a read or write operation; data is clocked in or
out of the chip on the negative edge of the clock
DB7 to DB0 data bus
the bi-directional, 3-state data bus transfers data between the system controller and
the PCF2103; DB7 may be used as the busy flag, signalling that internal operations
are not yet completed; in 4-bit operations the 4 higher order lines DB7 to DB4 are
used; DB3 to DB0 must be left open-circuit; there is an internal pull-up on each of the
data lines
C1 to C60 column driver
outputs
these pins output the data for columns
R1 to R18 row driver
outputs
these pins output the row select waveforms to the display; R17 and R18 drive the
icons
VLCD
LCD power
supply
positive power supply for the liquid crystal display
OSC
SCL
SDA
oscillator
serial clock line
serial data line
when the on-chip oscillator is used this pin must be connected to VDD; an external
clock signal, if used, is input at this pin
input for the I2C-bus clock signal
I/O for the I2C-bus data line
SA0
address pin
the hardware sub-address line is used to program the device sub-address for two
different PCF2103s on the same I2C-bus
T1
test pad
must be connected to VSS; not user accessible
PD power-down pad PD selects chip power-down mode; for normal operation PD = 0
Note
1. When the I2C-bus is used, the parallel interface pin E must be defined as E = 0. In I2C-bus read mode DB7 to DB0
should be connected to VDD or left open-circuit.
a) When the parallel bus is used, pins SCL and SDA must be connected to VSS or VDD; they may not be left
unconnected.
b) If the 4-bit interface is used without reading out from the PCF2103 (i.e. R/W is set permanently to logic 0), the
unused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.
1998 May 11
6

6 Page









PCF2103EU pdf, datenblatt
Philips Semiconductors
LCD controllers/drivers
Product specification
PCF2103 family
handbook, full pcahgaewraidctther codes
(DDRAM data)
76 5 43 2 10
higher
order
bits
lower
order
bits
00 0 00 0 00
00 0 00 0 01
00 0 00 0 10
CGRAM
address
6 5 43 2 10
higher
order
bits
lower
order
bits
00 0 00 0 0
001
010
011
100
101
110
111
00 0 10 0 0
001
010
011
100
101
110
111
0 0 1 00 0 0
001
00 0 01 1 11
00 0 01 1 11
00 0 01 1 11
00 0 01 1 11
1111100
1111101
1111110
1111111
character patterns
(CGRAM data)
4 3 21 0
higher
order
bits
lower
order
bits
0
0 00
0 00
0
0 00
00
0
0 00
0 0 00 0
0 00
0 00
00
00
00
00
00
00
0 0 00 0
character
pattern
example 1
cursor
position
character
pattern
example 2
character code
(CGRAM data)
4 3 21 0
1 1 11 0
1 0 00 1
1 0 00 1
1 1 11 0
1 0 10 0
1 0 01 0
1 0 00 1
0 0 00 0
1 0 00 1
0 1 01 0
1 1 11 1
0 0 10 0
1 1 11 1
0 0 10 0
0 0 10 0
0 0 00 0
MGE995
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with
the cursor. Data in the 8th position will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.6.
As shown in Figs 6 and 7, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds
to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in
the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address
counter’ command; see Table 7.
Fig.7 Relationship between CGRAM addresses and data and display patterns.
1998 May 11
12

12 Page





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