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PCF1174CU Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF1174CU
Beschreibung 4-digit static LCD car clock
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 20 Seiten
PCF1174CU Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF1174C
4-digit static LCD car clock
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC16
1997 Apr 16






PCF1174CU Datasheet, Funktion
Philips Semiconductors
4-digit static LCD car clock
Product specification
PCF1174C
12/24-hour mode
Operation in 12-hour or 24-hour mode is selected by
connecting MODE to VDD or VSS respectively.
Power-on
After connecting the supply, the start-up mode is:
1:00 AM; 12-hour mode.
0:00; 24-hour mode.
Colon
If FLASH is connected to VDD the colon pulses at 1 Hz.
If FLASH is connected to VSS the colon is static.
Time setting
Switch inputs S1 and S2 have a pull-up resistor to facilitate
the use of single-pole, single-throw contacts. A debounce
circuit is incorporated to protect against contact bounce
and parasitic voltages.
Set enable
Inputs S1 and S2 are enabled by connecting ENABLE to
VDD or disabled by connecting to VSS.
Set hours
When S1 is connected to VSS the hours displayed
advances by one and after one second continues with one
advance per second until S1 is released (auto-increment).
Set minutes
When S2 is connected to VSS the time displayed in
minutes advances by one and after one second continues
with one advance per second until S2 is released
(auto-increment). In addition to minute correction, the
seconds counter is reset to zero.
Segment test/reset
When S1 and S2 are connected to VSS, all LCD segments
are switched ON. Releasing switches S1 and S2 resets the
display. No reset occurs when DATA is connected to VSS
(overlapping S1 and S2).
Test mode
When TS is connected to VDD, the device is in normal
operating mode. When connecting TS to VSS all counters
(seconds, minutes and hours) are stopped, allowing quick
testing of the display via S1 and S2 (debounce and
auto-increment times are 64 times faster). TS has a
pull-up resistor but for reasons of safety it should be
connected to VDD.
EEPROM
VPP has a pull-up resistor but for reasons of safety it should
be connected to VDD.
LCD voltage programming
To enable LCD voltage programming, SEL is set to
open-circuit and a level of VDD 5 V is applied to VPP
(see Fig.6). The first pulse (tE) applied to the DATA input
clears the EEPROM to give the lowest voltage output.
Further pulses (tL) will increment the output voltage by
steps of typically 150 mV (Tamb = 25 °C).
For programming, measure VDD VSS and apply a store
pulse (tW) when the required value is reached. If the
maximum number of steps (n = 31) is reached and an
additional pulse is applied the voltage will return to the
lowest value.
Time calibration
To compensate for the tolerance in the quartz crystal
frequency which has been positively offset (nominal
deviation +60 × 106) by capacitors at the oscillator input
and output, a number (n) of 262144 Hz pulses are
inhibited every second of operation.
1997 Apr 16
6

6 Page









PCF1174CU pdf, datenblatt
Philips Semiconductors
4-digit static LCD car clock
Table 2 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to the bottom left pad (OSC IN), see Fig.7.
PAD
x y PAD
BP
PM
AM
ADEG1
C1
E2
D2
C2
E3
C3
E4
D4
C4
B4
S1
DATA
OSC IN
OSC OUT
VSS
MODE
chip corner (max. value)
600
400
200
0
138
138
138
138
138
138
138
138
138
138
138
138
0
200
400
600
360
2 676
2 676
2 676
2 676
2 448
2 228
2 008
1 808
1 608
1 408
1 208
1 008
808
608
388
168
0
0
0
0
170
VPP
TS
ENABLE
VDD
FLASH
SEL
S2
A4
F4
G4
B3
AD3
F3
G3
COL
B2
A2
F2
G2
B1
Product specification
PCF1174C
x
800
1 000
1 200
1 400
1 538
1 538
1 538
1 538
1 538
1 538
1 538
1 538
1 538
1 538
1 538
1 538
1 400
1 200
1 000
800
y
0
0
0
0
168
388
608
808
1 008
1 208
1 408
1 608
1 808
2 008
2 208
2 448
2 676
2 676
2 676
2 676
1997 Apr 16
12

12 Page





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