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PCD5096H Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCD5096H
Beschreibung Universal codec
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCD5096H Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCD5096
Universal codec
Preliminary specification
File under Integrated Circuits, IC17
1997 Jan 22






PCD5096H Datasheet, Funktion
Philips Semiconductors
Universal codec
Preliminary specification
PCD5096
SYMBOL
PIN
I/O(1)
DESCRIPTION
RESET
VSS_2
VDD_2
DI
DO
FSC
DCL
38 I reset input (Schmitt trigger)
39 P digital core ground supply
40 P 3 V digital core supply
41 I IOM-2 interface serial data input
42 O IOM-2 interface serial data output (open-drain)
43 I/O IOM-2 interface 8 kHz frame synchronization clock (Schmitt trigger input); note 2
44 I/O IOM-2 interface data clock (Schmitt trigger input); note 2
Note
1. ‘P’ denotes power line.
2. FSC and DCL are outputs only in test modes.
6.2 Pinning
handbook, full pagewidth
IO0 1
IO1 2
CLK 3
VDD_PLL 4
VSS_PLL 5
VSS_1 6
VDD_1 7
SCL 8
SDA 9
A0 10
A1 11
PCD5096
33 EARP_HS
32 VDDA_2
31 LIFM_AD2
30 LIFP_AD2
29 VSSA_2
28 MICM_HF
27 MICP_HF
26 VMIC_HF
25 MICM_HS
24 MICP_HS
23 VMIC_HS
MBH860
1997 Jan 22
Fig.2 Pin configuration.
6

6 Page









PCD5096H pdf, datenblatt
Philips Semiconductors
Universal codec
Preliminary specification
PCD5096
8.3 Control registers organization
8.3.1 CONTROL REGISTER ASSIGNMENT
The control register address assignment in the PCD5096 is shown in Table 3.
Table 3 Control register map
REGISTER
Control Register 0
Control Register 1
Control Register 2
Control Register 3
Control Register 4
Control Register 5
Control Register 6
REGISTER SIZE ADDRESS RESET STATE
MNEMONIC (BITS) (HEX)
(HEX)
FUNCTION
CR0
16
78
0000
control signals for codecs, codec test
modes, Power-down control and disable
phase correction
CR1 3 79
00 IOM control
CR2 16 7A
0000
gain setting of analog-to-digital (A/D) and
digital-to-analog (D/A) paths
CR3 16 7B
A0A0
reference voltage setting of Codec 1 and
Codec 2
CR4 16 7C
0000
selection of the DSP modes
CR5 2 7D
02 control of I/O pin IO0
CR6 2 7E
02 control of I/O pin IO1
1997 Jan 22
12

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