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PDF PCD5003AH Data sheet ( Hoja de datos )
| Número de pieza | PCD5003AH | |
| Descripción | Enhanced Pager Decoder for POCSAG | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCD5003A
Enhanced Pager Decoder for
POCSAG
Product specification
File under Integrated Circuits, IC17
1999 Jan 08
1 page  
Philips Semiconductors
Enhanced Pager Decoder for POCSAG
Product specification
PCD5003A
6 PINNING
SYMBOL PIN
DESCRIPTION
ATL 1 alert LOW-level output
ALC 2 alert control input (normally LOW by
internal pull-down)
DON
3 direct ON/OFF input (normally LOW by
internal pull-down)
REF
4 real-time clock frequency reference
output
INT 5 interrupt output
n.c. 6 not connected
RST
7 reset input (normally LOW by internal
pull-down)
VPR
SDA
SCL
8 external positive voltage reference
input
9 I2C-bus serial data input/output
10 I2C-bus serial clock input
VDD
VSS
VPO
CCP
11 main positive supply voltage
12 main negative supply voltage
13 voltage converter positive output
14 voltage converter shunt capacitor
(positive side)
CCN
15 voltage converter shunt capacitor
(negative side)
SYMBOL PIN
DESCRIPTION
TS1 16 test input 1 (normally LOW by internal
pull-down)
XTAL2 17 decoder crystal oscillator output
XTAL1 18 decoder crystal oscillator input
n.c. 19 not connected
TS2 20 test input 2 (normally LOW by internal
pull-down)
BAT 21 battery sense input
DQC
22 demodulator quick charge output
RDI 23 received POCSAG data input
RXE
24 receiver circuit enable output
ROE
25 receiver oscillator enable output
ZSD
26 synthesizer serial data output
ZSC
27 synthesizer serial clock output
ZLE 28 synthesizer latch enable output
VSS 29 main negative supply voltage
VIB 30 vibrator motor drive output
LED 31 LED drive output
ATH 32 alert HIGH-level output
handbook, full pagewidth
1999 Jan 08
ATL 1
ALC 2
DON 3
REF 4
INT 5
n.c. 6
RST 7
VPR 8
PCD5003AH
24 RXE
23 RDI
22 DQC
21 BAT
20 TS2
19 n.c.
18 XTAL1
17 XTAL2
MGL569
Fig.2 Pin configuration.
5
5 Page 
Philips Semiconductors
Enhanced Pager Decoder for POCSAG
Product specification
PCD5003A
7.16 Sync word indication
The sync word recognized by the PCD5003A is shown in
the call header (bits S3 to S1). The decimal value
represents the identifier number in the EEPROM of the
UPSW in question. A value of 7 indicates the standard
POCSAG sync word.
7.17 Error type indication
Table 10 shows how the different types of detected errors
are encoded in the call data output format.
A message code-word containing more than a single bit
error (bit E3 = 1) may appear as an address code-word
(bit M1 = 0) after error correction. In this event the
code-word is processed as message data and does not
cause call termination.
7.18 Data transfer
Data transfer is initiated either during sync word periods or
as soon as the receiver is disabled after call termination.
If the SRAM buffer is full, data transfer is initiated
immediately during the next code-word.
When the PCD5003A is ready to transfer received call
data an external interrupt will be generated via output INT.
Any message data can be read by accessing the RAM
output register via the I2C-bus interface. Bytes will be
output starting from the position indicated by the RAM read
pointer.
handbook, full pagewidth
1999 Jan 08
OFF to ON status
no preamble or
sync word
(3 batches)
switch-on
sync word
preamble
no preamble or
sync word
(1 batch)
preamble receive
sync word
data receive
sync word
no sync word
sync word
sync word
data fail
preamble
no preamble or
sync word
(1 batch)
fade recovery
preamble
no preamble or
sync word
(15 batches)
carrier off
preamble
MLC247
Fig.4 ACCESS® synchronization algorithm.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCD5003AH.PDF ] | |
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