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PCD5002H Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCD5002H
Beschreibung Advanced POCSAG and APOC-1 Paging Decoder
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCD5002H Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCD5002
Advanced POCSAG and APOC-1
Paging Decoder
Product specification
Supersedes data of 1997 Mar 04
File under Integrated Circuits, IC17
1997 Jun 24






PCD5002H Datasheet, Funktion
Philips Semiconductors
Advanced POCSAG and APOC-1 Paging
Decoder
Product specification
PCD5002
8 FUNCTIONAL DESCRIPTION
8.1 Introduction
The PCD5002 is a very low power decoder and pager
controller specifically designed for use in new generation
radio pagers. The architecture of the PCD5002 allows for
flexible application in a wide variety of radio pager designs.
The PCD5002 is fully compatible with “CCIR Radio paging
Code No. 1” (also known as the POCSAG code) operating
at data rates of 512, 1200 and 2400 bits/s using a single
oscillator crystal of 76.8 kHz.
The PCD5002 also supports the new Advanced Pager
Operator’s Code Phase 1 (APOC-1). This compatible
extension to the POCSAG code improves battery
economy by introducing ‘cycles’ and batch numbering.
A cycle consists of 5 or 15 standard POCSAG batches.
Each pager will be allocated a batch number in addition to
its POCSAG address and it will only search for its address
during this batch.
In addition to the standard POCSAG sync word (used also
in APOC-1) the PCD5002 is also capable of recognizing
up to 4 User Programmable Sync Words (UPSWs).
This permits the reception of both private services and
POCSAG or APOC-1 transmissions via the same radio
channel. As an option reception of a UPSW may activate
Continuous Data Decoding (CDD).
Used together with the Philips UAA2080 or UAA2082
paging receiver, the PCD5002 offers a highly
sophisticated, miniature solution for the radio paging
market. Control of an RF synthesizer circuit is also
provided to ease alignment and channel selection.
On-chip EEPROM provides storage for user addresses
(Receiver Identity Codes or RICs) and Special
Programmed Functions (SPFs) and UPSWs, which
eliminates the need for external storage devices and
interconnection. For other non-volatile storage 20 bytes of
general purpose EEPROM are available. The low
EEPROM programming voltage makes the PCD5002 well
suited for ‘over-the-air’ programming/reprogramming.
On request from an external controlling device or
automatically (by SPF programming), the PCD5002 will
provide standard POCSAG alert cadences by driving a
standard acoustic ‘beeper’. Non-standard alert cadences
may be generated via a cadence register or a dedicated
control input.
The PCD5002 can also produce a HIGH level acoustic
alert as well as drive an LED indicator and a vibrator motor
via external bipolar transistors.
The PCD5002 contains a low-power, high-efficiency
voltage converter (doubler) designed to provide a higher
voltage supply to LCD drivers or microcontrollers.
In addition, an independent level shifted interface is
provided allowing communication to a microcontroller
operating at a higher voltage than the PCD5002.
Interface to such an external device is provided by an
I2C-bus which allows received call identity and message
data, data for the programming of the internal EEPROM,
alert control and pager status information to be transferred
between the devices. Pager status includes features
provided by the PCD5002 such as battery-low and
out-of-range indications. A dedicated interrupt line
minimizes the required microcontroller activity.
A selectable low frequency timing reference is provided for
use in real time clock functions.
Data synchronization is achieved by the Philips patented
ACCESS® algorithm ensuring that maximum advantage is
made of the POCSAG code structure particularly in fading
radio signal conditions. The algorithm allows for data
synchronization without preamble detection whilst
minimizing battery power consumption. The APOC-1 code
uses an extended version of the ACCESS®
synchronization algorithm.
Random (and optional) burst error correction techniques
are applied to the received data to optimize the call
success rate without increasing the falsing rate beyond
specified POCSAG levels.
8.2 The POCSAG paging code
A transmission using the “CCIR Radio paging Code No. 1”
(POCSAG code) is constructed in accordance with the
following rules (see Fig.3).
The transmission is started by sending a preamble,
consisting of at least 576 continuously alternating bits
(10101010...). The preamble is followed by an arbitrary
number of batch blocks. Only complete batches are
transmitted.
Each batch comprises 17 codewords of 32 bits each.
The first codeword is a synchronization codeword with a
fixed pattern. The sync word is followed by 8 frames
(0 to 7) of 2 codewords each, containing message
information. A codeword in a frame can either be an
address, message or idle codeword.
Idle codewords also have a fixed pattern and are used to
fill empty frames or to separate messages.
1997 Jun 24
6

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PCD5002H pdf, datenblatt
Philips Semiconductors
Advanced POCSAG and APOC-1 Paging
Decoder
Product specification
PCD5002
After reception of any broadcast message data the
PCD5002 continues to operate in the ‘cycle receive’ mode.
In the cycle receive mode the PCD5002 enables call
reception in only one programmed batch per cycle. Sync
word detection takes place from 2 bits before to 2 bits after
the expected sync word position of this batch. If the sync
word is not detected then the position of the current sync
word will be maintained and the ‘short fade recovery’
mode will be entered.
When a valid sync word is found user address codeword
detection takes place, as in normal POCSAG code.
Any following message codewords are received normally.
If a message extends into a subsequent batch containing
a batch zero identifier, then the batch zero identifier is
detected normally and message reception will continue.
Data reception is suspended after the programmed batch
until the same batch position in the next cycle.
The exception being when a received call continues into
the next batch.
In the short fade recovery mode the programmed data
receive batch will continue to be checked for user address
codewords. In addition the first codeword after the
programmed batch is checked for sync word or preamble.
When a valid sync word is detected the ‘cycle receive’
mode is re-entered, while detection of preamble causes
the device to switch to the ‘preamble receive’ mode. When
neither is found then the ‘transmitter off’ mode is entered.
In the transmitter off mode a time-out is set to a
pre-programmed duration. This time-out corresponds to
the maximum time between subsequent transmissions
(preamble to preamble).
The PCD5002 then checks the first batch of every cycle for
sync word or preamble. The programmed data receive
batch is ignored (unless it is batch 0).
Table 4 Synchronization window tolerance as a function
of bit rate
TIME FROM
LOSS OF SIGNAL
30 s
60 s
120 s
240 s
TOLERANCE
512
(bits/s)
1 200
(bits/s)
2 400
(bits/s)
4 bits
4 bits
4 bits
8 bits
4 bits
4 bits
8 bits
16 bits
4 bits
8 bits
16 bits
32 bits
Synchronization checking is performed over a window
ranging from ‘n’ bits before to ‘n’ bits after the expected
sync word position. The window tolerance ‘n’ depends on
the time since the ‘transmitter off’ mode was entered and
on the selected bit rate (see Table 4).
When a sync word is detected in this widened
synchronization window the PCD5002 enters the
‘batch zero identify’ mode. Time-out expiry before a sync
word has been detected causes the device to switch to the
‘long fade recovery’ mode.
Detection of preamble in the ‘transmitter off’ mode initiates
the preamble receive 2 mode. Operation in this mode is
identical to ‘preamble receive mode. Failure to detect
preamble for one batch period will cause the device to
switch back to the ‘transmitter off’ mode. This prevents
inadvertent loss of cycle synchronization due to spurious
signals resembling preamble.
The carrier detect mode is identical to the ‘carrier off’
mode in standard POCSAG operation. Upon first entry the
transmitter off time-out is started. The receiver is enabled
to receive one codeword in every 18 codewords to check
for sync word and preamble. This check is performed on
the last available 32 bits for every received bit.
The ‘preamble receive’ mode is entered if preamble is
detected. If a valid sync word is found the
‘batch zero detect’ mode is entered. If neither has been
detected and the time-out expires, then the
‘long fade recovery’ mode is entered.
The long fade recovery mode is intended to quickly
regain synchronization in fading conditions (not caused by
the transmitter switching off between transmissions) or
when having been out of range, while maintaining
acceptable battery economy.
Initially, the receiver is switched off until one cycle duration
after the last enabling in the ‘transmitter off’ mode.
The receiver is then enabled for a 2 codeword period in
which each contiguous group of 32 bits is tested for any
decodable POCSAG codeword (including sync word) and
preamble. Single-bit error correction is applied.
If a codeword is detected, the receiver enable period is
extended by another codeword duration and the above
test is repeated. This process continues while valid
codewords are received.
Detection of preamble will cause the device to switch to the
‘preamble receive’ mode, while sync word detection will
cause the device to switch to the ‘batch zero detect’ mode.
When neither is detected during the 2 codeword window or
any following 32-bit group, the receiver will be disabled.
1997 Jun 24
12

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