PCD3360 Datasheet PDF - NXP Semiconductors
| Part Number | PCD3360 | |
| Description | Programmable multi-tone telephone ringer | |
| Manufacturers | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
PCD3360
Programmable multi-tone
telephone ringer
Product specification
Supersedes data of August 1985
File under Integrated Circuits, IC03
1997 Jan 15
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Philips Semiconductors
Programmable multi-tone telephone ringer
Product specification
PCD3360
7 FUNCTIONAL DESCRIPTION (see Fig.1)
7.1 Supply pins (VDD and VSS)
If the supply current (VDD) drops below the standby voltage
(Vstb), the oscillator and most other functions are switched
off and the supply current is reduced to the standby current
(Istb). The automatic swell register retains its information
until VDD drops further to a value VAS at which reset
occurs.
7.2 Oscillator (OSC)
The 64 kHz oscillator is operated via an external resistor
and capacitor connected to pin OSC (see Fig.8).
The oscillator signal is divided by two to provide the 32 kHz
internal system clock.
7.3 Selection pin input circuit (see Fig.3)
Pins FDE, RR1, RR2, DM, IS1, IS2, TS1, TS2, FL and FH
are pulled down internally by a pull-down current IIH when
they are connected to VDD and by a pull-down resistance
RIL when they are connected to VSS. Thus when the pins
are open-circuit they are defined LOW. Therefore only a
single-contact switch is required to connect the pins to
VDD; yet the supply current is only marginally increased as
IIH is very small.
selection
pins
FDE
RR1
RR2
DM
IS1
IS2
TS1
TS2
FL
FH
IIH
(1)
VSS
PCD3360
MGD709
7.4 Frequency discriminator circuit (FDE and FDI)
The frequency discriminator circuit prevents the ringer
being activated unintentionally by dial pulses, speech or
other invalid signals.
The circuit is enabled or disabled by input FDE. When FDE
is LOW and VDD > Vstb, the circuit is enabled and FDI acts
as the input for ringing frequency detection. When FDE is
HIGH, the circuit is disabled and FDI becomes the
enable/disable input for tone sequence generation.
When the circuit is enabled, it starts to produce output
ringing tones after one cycle of an appropriate input
frequency is detected at FDI. An input cycle is detected
when either 2 rising or 2 falling edges are received, and
this implies a delay of between 1 and 1.5 input cycles
before output ringing begins. The allowed input frequency
range is set by the states of pins FL and FH, as shown in
Table 2. Output ringing continues for as long as valid input
ringing frequency is detected.
FDI has a Schmitt-trigger action; the levels are set by an
external resistor R2 (see Fig.8) and an internal sink current
that is switched from 20 µA (typ.) for FDI = LOW to <0.1 µA
for FDI = HIGH. Excess current entering FDI via R2 is
absorbed by internal diodes clamped to VDD and VSS.
7.5 Selection of frequency discriminator limits
(FL and FH)
With the frequency discriminator enabled (VDD > Vstb and
FDE = LOW) the lower and upper limits of the input
frequency are set by the inputs FL and FH as shown by
Table 2.
Table 2 Selection of lower and upper frequency
discriminator limits (fOSC = 64 kHz)
FL INPUT
STATE
LOWER
LIMIT
FH INPUT
STATE
UPPER
LIMIT
LOW
HIGH
20 Hz
13.3 Hz
LOW
HIGH
60 Hz
30 Hz
(1) Transistor resistance is RIL when switched on.
Fig.3 Input circuit of selection pins.
1997 Jan 15
5
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| Information | Total 20 Pages | |
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| Download | [ PCD3360.PDF Datasheet ] | |
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