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PCD3311C Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCD3311C
Beschreibung DTMF/modem/musical-tone generators
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 28 Seiten
PCD3311C Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCD3311C; PCD3312C
DTMF/modem/musical-tone
generators
Product specification
Supersedes data of May 1990
File under Integrated Circuits, IC03
1996 Nov 21






PCD3311C Datasheet, Funktion
Philips Semiconductors
DTMF/modem/musical-tone generators
Product specification
PCD3311C; PCD3312C
7 FUNCTIONAL DESCRIPTION
7.1 General (see Fig.1)
The Input Control Logic decodes the input data to
determine whether DTMF, modem or musical tones are
selected; and which particular tone or combination of
tones is required.
A code representing the required tones is sent to the
Divider Selection ROM which selects the correct division
ratio in both of the Frequency Dividers (or in one divider, if
only a single tone is required).
The Oscillator circuit provides a square wave of frequency
3.58 MHz. Each Frequency Divider divides the frequency
of the Oscillator to give a serial digital square wave with a
frequency simply related to that of the required tone.
The output from each Frequency Divider goes to a DAC,
which is also fed by a clock derived from the oscillator.
Using these two signals, the DAC produces an
approximate sine wave of the required frequency, with an
amplitude derived from the Voltage Reference.
The output from the DAC goes to an Adder where, for
DTMF, it is combined with the output from the other DAC.
The output from the Adder goes through two stages of Low
Pass Filters to give a smoothed tone (single or dual), and
finally to the TONE output.
7.4 Data inputs (PCD3311C)
Inputs D0, D1, D2, D3, D4 and D5 are used in the parallel
data input mode of the PCD3311C. Inputs D0 and D1 are
also used in serial input mode when they act as the SCL
and SDA inputs respectively. Inputs D0 and D1 have no
internal pull-down or pull-up resistors and must not be left
open in any application. Inputs D2, D3, D4 and D5 have
internal pull-down.
D4 and D5 are used to select between DTMF dual, DTMF
single, modem and musical tones (see Table 1). D0, D1,
D2 and D3 select the tone combination or single tone
within the selected application. They also, in combination
with D4, select the standby mode. See Tables 2, 3, 4
and 5.
PCD 3312C has no parallel data pins as data input is via
the I2C-bus.
Table 1 Use of D5 and D4 to select application
D5 D4
APPLICATION
LOW LOW DTMF single tones; musical tones;
standby
LOW HIGH DTMF dual tones (all 16 combinations)
HIGH LOW modem tones
HIGH HIGH musical tones
7.2 Clock/oscillator connection
The timebase for the PCD3311C and PCD3312C is a
crystal-controlled oscillator, requiring a 3.58 MHz quartz
crystal to be connected between OSCI and OSCO.
Alternatively, the OSCI input can be driven from an
external clock of 3.58 MHz.
7.3 Mode selection (PCD3311C)
The MODE input selects the data input mode for the
PCD3311C. When MODE is connected to VDD (HIGH),
data can be received in the parallel mode. When
connected to VSS (LOW) or left open, data can be received
via the serial I2C-bus.
PCD 3312C has no MODE input as data input is via the
I2C-bus only.
7.5 Strobe input (PCD3311C )
The STROBE input (with internal pull-down) allows the
loading of parallel data into D0 to D5 when MODE is HIGH.
The data inputs must be stable preceding the
positive-going edge of the strobe pulse (active HIGH).
Input data are loaded at the negative-going edge of the
strobe pulse and then the corresponding tone (or standby
mode) is provided at the TONE output. The output remains
unchanged until the negative-going edge of the next
STROBE pulse (for new data) is received. Figure 5 is an
example of the timing relationship between STROBE and
the data inputs.
When MODE is LOW, data is received serially via the
I2C-bus.
1996 Nov 21
6

6 Page









PCD3311C pdf, datenblatt
Philips Semiconductors
DTMF/modem/musical-tone generators
Product specification
PCD3311C; PCD3312C
8.3 System configuration (see Fig.9)
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
message transfer is the ‘master’ and the devices that are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
Fig.9 System configuration.
MASTER
TRANSMITTER /
RECEIVER
MBA605
8.4 Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited.
Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the
transmitter whereas the master generates an extra acknowledge after the reception of each byte. Also a master must
generate an acknowledge after reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the acknowledge-related clock pulse. Set-up and hold times must
be taken into account to ensure that the SDA line is stable LOW during the whole HIGH period of the
acknowledge-related clock pulse. A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate the stop condition.
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
S
START
CONDITION
1
not acknowledge
acknowledge
2 89
MBC602
clock pulse for
acknowledgement
Fig.10 Acknowledgment on the I2C-bus.
1996 Nov 21
12

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