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PC97317 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer PC97317
Beschreibung PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
PC97317 Datasheet, Funktion
- February 1998
PRELIMINARY
February 1998
PC87317VUL/PC97317VUL SuperI/O Plug and Play
Compatible with ACPI Compliant Controller/Extender
Highlights
General Description
The PC87317VUL/PC97317VUL are functionally identical
parts that offer a single-chip solution to the most commonly
used ISA, EISA and MicroChannel® peripherals. This fully
Plug and Play (PnP) compatible chip conforms to the Plug
and Play ISA Specification Version 1.0a, May 5, 1994, and
meets specifications defined in the PC97 Hardware Design
Guide. It features a Controller/Extender that is fully compli-
ant with Advanced Configuration and Power Interface (AC-
PI) Revision 1.0 requirements.
Note: All references to the PC87317VUL in this document
also refer to the PC97317VUL, unless otherwise specified.
References which are applicable to the PC97317VUL only
are italicized.
The PC87317VUL incorporates: an advanced Real-Time
Clock (RTC) device that provides both RTC timekeeping and
Advanced Power Control (APC) functionality, a Floppy Disk
Controller (FDC), a Keyboard and Mouse Controller (KBC),
two enhanced Serial Ports (UARTs) with Infrared (IR) sup-
port, a full IEEE 1284 Parallel Port, 24 General-Purpose In-
put/Output (GPIO) bit ports, three general-purpose chip
select signals that can be programmed for game port control
and a separate configuration register set for each module.
The PC87317VUL provides a LED drive output to comply
with PC97 specifications. The chip also provides support for
Power Management (PM), including a WATCHDOGtimer,
and standard PC-AT address decoding for on-chip functions.
The PC87317VUL Infrared (IR) interface complies with the
HP-SIR and SHARP-IR standards, and supports all four ba-
sic protocols for Consumer Remote Control circuitry (RC-5,
RC-5 extended, RECS80 and NEC).
Outstanding Features
Among the most advanced members of National Semicon-
ductor’s highly successful SuperI/O family, the PC87317VUL
offers:
q Full compatibility with ACPI Revision 1.0 requirements
q Compliancy with PC97 Hardware Design Guide speci-
fications, including PC97 LED support
q Advanced RTC, including timekeeping and APC func-
tionality
q 24 GPIO bit ports
q FDC, KBC, two enhanced UARTs, IR support, IEEE
1284 parallel port
Block Diagram
DMA
IRQ Channels
Data and
Control Ports
Control
Data Control
Floppy Drive
Interface
Plug and Play
(PnP)
Keyboard + Mouse
Controller (KBC)
(Logical Devices 0 & 1)
Real-Time Clock
(RTC and APC)
(Logical Device 2)
X-Bus
Floppy Disk
Controller (FDC)
(Logical Device 3)
µP Address
Data and
Control
IEEE 1284
Serial Port
Serial Port
General-Purpose I/O
Power
Parallel Port
with IR (UART2)
(UART1)
(GPIO) Registers Management (PM)
(Logical Device 4) (Logical Devices 5) (Logical Devices 6) (Logical Device 7) (Logical Device 8)
Data Handshake Serial Infrared
Interface Interface
Serial
Interface
I/O Ports
Control
TRI-STATE® and WATCHDOGare trademarks of National Semiconductor Corporation.
IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
© 1998 National Semiconductor Corporation
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PC97317 Datasheet, Funktion
Table of Contents
2.10.6 CS1 Base Address LSB Register ................................................................................ 43
2.10.7 CS1 Configuration Register ......................................................................................... 43
2.10.8 Reserved ..................................................................................................................... 44
2.10.9 CS2 Base Address MSB Register ............................................................................... 44
2.10.10 CS2 Base Address LSB Register ................................................................................ 44
2.10.11 CS2 Configuration Register ......................................................................................... 44
2.10.12 Reserved, Second Level Indexes 0Bh-0Fh ................................................................. 44
2.10.13 Not Accessible, Second Level Indexes 10h-FFh ......................................................... 44
2.11 CONFIGURATION REGISTER BITMAPS ................................................................................ 44
3.0 Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
3.1 SYSTEM ARCHITECTURE ....................................................................................................... 47
3.2 FUNCTIONAL OVERVIEW ....................................................................................................... 48
3.3 DEVICE CONFIGURATION ...................................................................................................... 48
3.3.1 I/O Address Space ...................................................................................................... 48
3.3.2 Interrupt Request Signals ............................................................................................ 48
3.3.3 KBC Clock ................................................................................................................... 49
3.3.4 Timer or Event Counter ............................................................................................... 50
3.4 EXTERNAL I/O INTERFACES .................................................................................................. 50
3.4.1 Keyboard and Mouse Interface ................................................................................... 50
3.4.2 General Purpose I/O Signals ....................................................................................... 50
3.5 INTERNAL KBC - PC87317VUL INTERFACE .......................................................................... 51
3.5.1 The KBC DBBOUT Register, Offset 60h, Read Only .................................................. 52
3.5.2 The KBC DBBIN Register, Offset 60h (F1 Clear) or 64h (F1 Set), Write Only ............ 52
3.5.3 The KBC STATUS Register ........................................................................................ 52
3.6 INSTRUCTION TIMING ............................................................................................................. 52
4.0 Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
4.1 RTC OVERVIEW ....................................................................................................................... 53
4.1.1 RTC Hardware and Functional Description ................................................................. 53
4.1.2 Timekeeping ................................................................................................................ 54
4.1.3 Power Management .................................................................................................... 55
4.1.4 Interrupt Handling ........................................................................................................ 56
4.2 THE RTC REGISTERS ............................................................................................................. 56
4.2.1 RTC Control Register A (CRA) .................................................................................... 56
4.2.2 RTC Control Register B (CRB) .................................................................................... 57
4.2.3 RTC Control Register C (CRC) ................................................................................... 58
4.2.4 RTC Control Register D (CRD) ................................................................................... 58
4.2.5 Date-of-Month Alarm Register (DMAR ........................................................................ 59
4.2.6 Month Alarm Register (MAR) ...................................................................................... 59
4.2.7 Century Register (CR) ................................................................................................. 59
4.3 APC OVERVIEW ....................................................................................................................... 59
4.3.1 System Power States .................................................................................................. 61
4.3.2 System Power Switching Logic ................................................................................... 62
4.4 APC DETAILED DESCRIPTION ............................................................................................... 62
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PC97317 pdf, datenblatt
Table of Contents
7.16.2
7.16.3
7.16.4
(LCR/BSR) Register .................................................................................................. 183
Infrared Control Register 2 (IRCR2) .......................................................................... 183
Reserved Registers ................................................................................................... 183
7.17 BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS ......................... 183
7.17.1 Infrared Control Register 3 (IRCR3) .......................................................................... 183
7.17.2 Reserved Register ..................................................................................................... 184
7.17.3 SIR Pulse Width Register (SIR_PW) ......................................................................... 184
7.17.4 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 184
7.17.5 Reserved Registers ................................................................................................... 184
7.18 BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS 184
7.18.1 Infrared Receiver Demodulator Control Register (IRRXDC) ..................................... 184
7.18.2 Infrared Transmitter Modulator Control Register (IRTXMC) ...................................... 185
7.18.3 Consumer-IR Configuration Register (RCCFG), ....................................................... 187
7.18.4 Link Control/Bank Select Registers (LCR/BSR) ........................................................ 188
7.18.5 Infrared Interface Configuration Register 1 (IRCFG1) ............................................... 188
7.18.6 Reserved Register ..................................................................................................... 189
7.18.7 Infrared Interface Configuration 3 Register (IRCFG3) ............................................... 189
7.18.8 Infrared Interface Configuration Register 4 (IRCFG4) ............................................... 189
7.19 UART2 WITH IR REGISTER BITMAPS .................................................................................. 190
8.0 Enhanced Serial Port - UART1 (Logical Device 6)
8.1 REGISTER BANK OVERVIEW ............................................................................................... 195
8.2 DETAILED DESCRIPTION ...................................................................................................... 195
8.2.1 16450 or 16550 UART Mode ..................................................................................... 196
8.2.2 Extended UART Mode ............................................................................................... 196
8.3 FIFO TIME-OUTS .................................................................................................................... 196
8.4 AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE .......................................... 197
8.4.1 Transmission Deferral ............................................................................................... 197
8.5 BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS ................................................. 197
8.5.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD) ................................. 197
8.5.2 Interrupt Enable Register (IER) ................................................................................. 198
8.5.3 Event Identification Register (EIR) ............................................................................ 199
8.5.4 FIFO Control Register (FCR) ..................................................................................... 200
8.5.5 Line Control Register (LCR) and Bank Selection Register (BSR) ............................. 201
8.5.6 Bank Selection Register (BSR) ................................................................................. 202
8.5.7 Modem/Mode Control Register (MCR) ...................................................................... 203
8.5.8 Line Status Register (LSR) ........................................................................................ 204
8.5.9 Modem Status Register (MSR) .................................................................................. 205
8.5.10 Scratchpad Register (SPR) ....................................................................................... 205
8.5.11 Auxiliary Status and Control Register (ASCR) .......................................................... 205
8.6 BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS ......................................... 206
8.6.1 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), .............................. 206
8.6.2 Line Control Register (LCR) and Bank Select Register (BSR) .................................. 207
8.7 BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................ 207
8.7.1 Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ........................... 207
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