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PC87591L Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer PC87591L
Beschreibung LPC Mobile Embedded Controllers
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 70 Seiten
PC87591L Datasheet, Funktion
PRELIMINARY
March 2004
Revision 1.07
PC87591E, PC87591S and PC87591L
LPC Mobile Embedded Controllers
General Description
The National Semiconductor PC87591E, PC87591S and
PC87591L are highly integrated, embedded controllers with
an embedded-RISC core and integrated advanced func-
tions. These devices are targeted for a wide range of porta-
ble applications that use the Low Pin Count (LPC) interface.
The PC87591S is targeted for security applications and in-
cludes supporting hardware such as the Hardware Random
Number Generator. The PC8591L replaces the on-chip
flash with 4K of boot ROM for value solutions using shared
BIOS architecture. “PC87591x” refers to all the devices.
The PC87591x incorporates National’s CompactRISC
CR16B core (a high-performance 16-bit RISC processor),
on-chip flash (ROM for the PC87591L) and RAM memories,
system support functions and a Bus Interface Unit (BIU) that
directly interfaces with optional external memory (such as
flash) and I/O devices.
System support functions include: WATCHDOG and other
timers, interrupt control, general-purpose I/O (GPIO) with
internal keyboard matrix scanning, PS/2® Interface,
ACCESS.bus® interface, high accuracy analog-to-digital
(ADC) and digital-to-analog converters (DAC) for battery
charging, system control, system health monitoring and an-
alog controls.
The PC87591x interfaces with the host via an LPC interface
that provides the host with access to the Keyboard and em-
bedded controller interface channels, integrated functions,
Real-Time Clock (RTC), BIOS firmware and security func-
tions.
Like members of National’s SuperI/O family, the PC87591x
is PC01 and ACPI compliant.
Outstanding Features
Host interface, based on Intel’s LPC Interface Specifi-
cation Revision 1.0, September 29th, 1997
PC01 Rev 1.0, and ACPI 2.0 compliant
16-bit RISC core, with 2 Mbyte address space, and
running at up to 20 MHz
Software and Hardware controlled clock throttling
Shared BIOS flash memory (internal and/or external)
Y2K-compliant RTC
84/117 GPIO ports (for 128-pin/176-pin packages)
with a variety of wake-up events
Extremely low current consumption in Idle mode
JTAG-based debugger interface
128-pin and 176-pin options, in LQFP package
(PC87591L is 176-pin only)
Block Diagram
LPC Serial
I/F IRQ SMI
Reset &
Config
CR16B Core
Processing
Unit
DMA
Host
Controlled
Functions
LPC Bus I/F
Internal Bus
Core Bus
I/F Functions
CR Access Shared mem. Bus
Bridge
+ Security Adapter
Memory
RAM FLASH or ROM
BIU
Peripheral Bus
Peripherals
KBC + PM
Host I/F
MSWC
HFCG
ICU
KBSCAN +
ACM
GPIO
ACB
(X2)
Timer +
WDG
ADC USART
RTC
32.768 KHz
PMC MIWU
CLK
Debugger PS/2
I/F I/F
MFT16
(X2)
PWM
DAC
JTAG
External
Memory + I/O
National Semiconductor is a registered trademark of National Semiconductor Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders.
© 2004 National Semiconductor Corporation
www.national.com






PC87591L Datasheet, Funktion
Table of Contents
Embedded Controller System Features ................................................................. 2
Host Controlled Functions Features ...................................................................... 3
Clocking, Supply and Package Information ........................................................... 4
Revision Record .................................................................................................... 5
1.0 Introduction
1.1 DOCUMENT ORGANIZATION .................................................................................................. 23
1.2 GENERAL DESCRIPTION ........................................................................................................ 23
1.2.1 System Connections .................................................................................................... 23
1.2.2 Power Management .................................................................................................... 23
1.2.3 Operating Environments .............................................................................................. 25
1.3 INTERNAL ARCHITECTURE .................................................................................................... 25
1.3.1 Processing Unit ........................................................................................................... 26
1.3.2 Bus Interface Unit and Memory Controller (BIU) ......................................................... 26
1.3.3 On-Chip Memory ......................................................................................................... 26
1.3.4 Peripherals .................................................................................................................. 27
1.3.5 Host-Controller Interface Modules ............................................................................... 28
1.3.6 Host-Controlled SuperI/O Modules and Host Interface ............................................... 29
1.4 OPERATING ENVIRONMENTS ................................................................................................ 29
1.4.1 IRE Environment ......................................................................................................... 29
1.4.2 OBD Environment ........................................................................................................ 30
1.4.3 DEV Environment ........................................................................................................ 30
1.4.4 PROG Environment ..................................................................................................... 30
1.5 MEMORY MAP .......................................................................................................................... 30
1.5.1 Core Address Domain Memory Map ........................................................................... 33
Register Abbreviations and Access ..................................................................... 34
Accessing Base Memory ..................................................................................... 35
Accessing Expansion Memory ............................................................................. 36
Accessing I/O Expansion Space .......................................................................... 37
1.5.2 Host Address Domain Memory Map ............................................................................ 38
1.5.3 Core Access to Host Controlled Peripherals ............................................................... 38
2.0 Signal/Pin Description and Configuration
2.1 CONNECTION DIAGRAMS ...................................................................................................... 39
2.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 41
2.2.1 ACCESS.bus (ACB1 and ACB2) Interface .................................................................. 42
2.2.2 Analog Interface .......................................................................................................... 42
2.2.3 Clocks .......................................................................................................................... 42
2.2.4 Core Bus Interface Unit (BIU) ...................................................................................... 43
2.2.5 Development System Support ..................................................................................... 44
2.2.6 General-Purpose I/O (GPIO) and Internal Keyboard Scan ......................................... 45
2.2.7 Host Interface .............................................................................................................. 48
2.2.8 Interrupt and Wake-Up Inputs (ICU and MIWU) .......................................................... 49
2.2.9 Power and Ground ...................................................................................................... 49
2.2.10 PS/2 Interface .............................................................................................................. 50
2.2.11 Strap Configuration ...................................................................................................... 50
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PC87591L pdf, datenblatt
Table of Contents (Continued)
4.11.6
4.11.7
Initializing the ADC ............................................................................................ 174
Enabling and Disabling the ADC ....................................................................... 174
Interrupt Structure .............................................................................................. 175
ADC Operating Principles .................................................................................. 175
Reading Measurement Results ......................................................................... 176
Failure Detection ................................................................................................ 177
ADC Registers ........................................................................................................... 177
ADC Register Map ............................................................................................. 177
ADC Status Register (ADCSTS) ........................................................................ 178
ADC Configuration Register (ADCCNF) ............................................................ 179
ADC Clock Control Register (ACLKCTL) ........................................................... 179
ADC Delay Control Register (ADLYCTL) .......................................................... 180
Local Diode Overtemperature Limit Register (TLOCOTL) ................................. 181
ADC Parameters Index Register (ADCPINX) .................................................... 181
ADC Parameters Data Register (ADCPD) ......................................................... 181
Temperature Channel Control Register (TCHANCTL) ...................................... 182
Temperature Channel Data Buffer (TCHANDAT) .............................................. 182
Voltage Channel 1 Control Register (VCHN1CTL) ............................................ 183
Voltage Channel 1 Data Buffer (VCHN1DAT) ................................................... 184
Voltage Channel 2 Control Register (VCHN2CTL) ............................................ 184
Voltage Channel 2 Data Buffer (VCHN2DAT) ................................................... 184
Voltage Channel 3 Control Register (VCHN3CTL) ............................................ 185
Voltage Channel 3 Data Buffer (VCHN3DAT) ................................................... 185
Usage Hints ............................................................................................................... 185
Power Supply and Layout Guidelines ................................................................ 185
Power Consumption .......................................................................................... 185
Back-Drive Protection ........................................................................................ 185
Measuring Out of Range Voltages ..................................................................... 185
Filtering the Noise on Voltage Input Signals ...................................................... 186
Calculating the Voltage Channel Delay ............................................................. 186
Thermistor-Based Temperature Measurement .................................................. 186
Remote Diode Selection .................................................................................... 187
Filtering the Noise on Temperature Input Signals ............................................. 187
Calculating the Temperature Channel Delay ..................................................... 188
PC Board Layout ............................................................................................... 188
Twisted Pair and Shielded Cables ..................................................................... 189
4.12 DIGITAL TO ANALOG CONVERTER (DAC) .......................................................................... 190
4.12.1 Features .................................................................................................................... 190
4.12.2 Functional Description ............................................................................................... 190
4.12.3 D/A Conversion ......................................................................................................... 190
Output Signal ..................................................................................................... 190
Reference Voltage ............................................................................................. 191
Conversion Time ................................................................................................ 191
4.12.4 Operation ................................................................................................................... 192
Initializing the DAC ............................................................................................ 192
Enabling and Disabling the DAC ....................................................................... 192
4.12.5 DAC Registers ........................................................................................................... 193
DAC Register Map ............................................................................................. 193
DAC Control Register (DACCTRL) .................................................................... 193
DAC Data Channel 0-3 Registers (DACDAT0-3) .............................................. 194
4.12.6 Usage Hints ............................................................................................................... 194
Power Consumption .......................................................................................... 194
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