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PDF PC87570 Data sheet ( Hoja de datos )
| Número de pieza | PC87570 | |
| Descripción | PC87570 Keyboard and Power Management Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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- January 1998
PRELIMINARY
April 1998
PC87570 Keyboard and Power Management Controller
Highlights
General Description
The PC87570 is a highly integrated embedded RISC-based
controller optimized for power management (PM), keyboard
and mouse (KBC) and system control in portable Personal
Computer (PC) applications.
The PC87570 incorporates National’s CompactRISC™
CR16A core, a high performance 16-bit RISC processor
core, a Bus Interface Unit (BIU) that directly interfaces with
memory and I/O devices, on-chip memory and system sup-
port functions. Among these are legacy functions, handled
by the Host Bus Interface (HBI), that include the Real-Time
Clock and Advanced Power Control (RTC and APC), and
peripherals, including: frequency-multiplier-based High Fre-
quency Clock Generator (HFCG), Power Mode Control
(PMC), Interrupt Control Unit (ICU), Multi-Input Wake-Up
(MIWU), General Purpose I/O Ports (GPIO) with internal
keyboard matrix scanning, PS/2® Interface, ACCESS.bus®
Block Diagram
(ACB) Interface, two Multi-Function 16-Bit Timers (MFT16),
periodic interrupt timer and WATCHDOG™ (TWD), ADC
and DAC.
The PC87570 highly efficient architecture and its on-chip
peripherals, supporting functions and low power consump-
tion, provide a highly integrated solution for portable note-
book PCs, sub-notebook PCs and other portable devices.
Outstanding Features
q Shared BIOS memory
q Fully ACPI-compliant embedded controller
q Proprietary PS/2 shift mechanism
q Extremely low current consumption in Idle mode
q Support for a variety of off-chip wake-up sources
q Scalable design for growth without controller upgrade
CR16A Core
Processing
Unit
Core Bus
Bus
Adapter
Memory
RAM
ROM
Peripheral Bus
BIU
Host KBC + PM RTC +
Config Host I/F APC
Legacy
HBI
HFCG
ICU
GPIO
KBSCAN
ACB
I/F
Timer +
WDG
DAC
PMC
CLK
Peripherals
MIWU
PS/2
I/F
MFT16
(X2)
ADC
Host Bus
32.768
(ISA Compatible) KHz
CompactRISCTM, WATCHDOGTM and TRI-STATE® are trademarks of National Semiconductor Corporation.
IBM®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
ACCESS.bus® is a registered trademark of Digital Equipment Corporation.
I2C® is a registered trademark of Philips.
© 1998 National Semiconductor Corporation
1
External
Memory
+ I/O
www.national.com
1 page  
Table of Contents
3.2.3 Byte Accessing ............................................................................................................ 34
3.3 CLOCK AND BUS CYCLES ...................................................................................................... 34
3.3.1 Clock Cycles ................................................................................................................ 34
3.3.2 Control Signals ............................................................................................................ 35
3.3.3 Early Write Bus Cycle .................................................................................................. 36
3.3.4 Late Write Bus Cycle ................................................................................................... 38
3.3.5 Normal Read Bus Cycle .............................................................................................. 40
3.3.6 Fast Read Bus Cycle ................................................................................................... 42
3.3.7 I/O Expansion Bus Cycles ........................................................................................... 43
3.3.8 I/O Expansion Example ............................................................................................... 44
3.4 DEVELOPMENT SUPPORT ..................................................................................................... 44
3.4.1 Bus Status Signals ...................................................................................................... 44
3.4.2 Core Bus Monitoring .................................................................................................... 44
3.5 BIU REGISTERS ....................................................................................................................... 45
3.5.1 BIU Configuration Register (BCFG) ............................................................................ 45
3.5.2 I/O Zone Configuration Register (IOCFG) ................................................................... 45
3.5.3 Static Zone Configuration Register (SZCFGn) ............................................................ 45
3.6 USAGE HINTS .......................................................................................................................... 46
4.0 On-Chip Memory
4.1 INTERNAL RAM ........................................................................................................................ 47
4.2 INTERNAL ROM ........................................................................................................................ 47
4.2.1 Access Times .............................................................................................................. 47
4.2.2 ROM Shadow .............................................................................................................. 47
5.0 Host Bus Interface (HBI)
5.1 FEATURES ................................................................................................................................ 48
5.2 HOST ACCESS TO SHARED MEMORY DEVICE ................................................................... 49
5.2.1 Enabling Shared Memory Mode .................................................................................. 49
5.2.2 Memory Device Interface ............................................................................................. 49
5.2.3 Host Access to Shared Memory .................................................................................. 49
5.3 CORE ACCESS TO RTC/APC .................................................................................................. 49
5.3.1 Host and CR16A Arbitration over RTC/APC ............................................................... 49
5.4 USAGE HINTS .......................................................................................................................... 49
5.4.1 Shared Memory ........................................................................................................... 49
5.4.2 Wake-Up from Host ..................................................................................................... 50
5.4.3 Host Power-on Indication ............................................................................................ 50
5.5 HOST ACCESS TO PC87570 RESIDENT I/O DEVICES ......................................................... 50
5.5.1 Host Access to Configuration Registers ...................................................................... 50
5.5.2 Host Access to Resident I/O Devices .......................................................................... 50
5.5.3 Host Bus I/O Cycles .................................................................................................... 50
5.6 KBC CHANNEL ......................................................................................................................... 50
5.6.1 Status Register ............................................................................................................ 50
5.6.2 DBBOUT Register ....................................................................................................... 51
5.6.3 DBBIN Register ........................................................................................................... 51
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5 Page 
Table of Contents
14.3.4 Slow Speed Clock ..................................................................................................... 107
14.3.5 Counter Clock Source Select .................................................................................... 108
14.4 TIMER/COUNTER AND ACTION UNIT .................................................................................. 108
14.4.1 Operation Modes ....................................................................................................... 108
14.4.2 Timer Interrupts ......................................................................................................... 113
14.4.3 Timer I/O Functions ................................................................................................... 113
14.5 MFT16 REGISTERS ................................................................................................................ 114
14.5.1 Clock Prescaler Register (TPRSC) ........................................................................... 114
14.5.2 Clock Unit Control Register (TCKC) .......................................................................... 114
14.5.3 Timer/Counter Register 1 (TCNT1) ........................................................................... 114
14.5.4 Timer/Counter Register 2 (TCNT2) ........................................................................... 114
14.5.5 Reload/Capture Register A(TCRA) ........................................................................... 114
14.5.6 Reload/Capture Register B (TCRB) .......................................................................... 114
14.5.7 Timer Mode Control Register (TCTRL) ..................................................................... 114
14.5.8 Timer Interrupt Control Register (TICTL) ................................................................... 115
14.5.9 Timer Interrupt Clear Register (TICLR) ..................................................................... 115
15.0 Timer and WATCHDOG (TWD)
15.1 FEATURES .............................................................................................................................. 116
15.2 FUNCTIONAL DESCRIPTION ................................................................................................ 116
15.2.1 Input Clock ................................................................................................................. 116
15.2.2 Pre-Scale ................................................................................................................... 116
15.2.3 TWD Timer 0 ............................................................................................................. 116
15.3 WATCHDOG OPERATION .................................................................................................... 117
15.4 TWD CONTROL AND CONFIGURATION .............................................................................. 117
15.5 OPERATION IN IDLE MODE .................................................................................................. 117
15.6 TWD REGISTERS ................................................................................................................... 117
15.6.1 Timer and WATCHDOG Configuration Registers (TWCFG) ..................................... 117
15.6.2 Timer and Watchdog Clock Pre-Scaler Register (TWCP) ......................................... 117
15.6.3 TWD Timer 0 Register (TWDT0) ............................................................................... 118
15.6.4 TWDT0 Control and Status Register (T0CSR) .......................................................... 118
15.6.5 WATCHDOG Count Register (WDCNT) ................................................................... 118
15.6.6 WATCHDOG Service Data Match Register (WDSDM) ............................................. 118
15.7 USAGE HINTS ........................................................................................................................ 118
16.0 Analog to Digital Converter (ADC)
16.1 FEATURES .............................................................................................................................. 119
16.2 FUNCTIONAL DESCRIPTION ................................................................................................ 119
16.2.1 Reset ......................................................................................................................... 120
16.2.2 Reference Voltage ..................................................................................................... 120
16.2.3 Input Signal Range .................................................................................................... 120
16.2.4 ADC Clock ................................................................................................................. 120
16.2.5 Initializing and Enabling the ADC .............................................................................. 120
16.2.6 ADC Operation .......................................................................................................... 121
16.2.7 Disabling the ADC to Save Power ............................................................................. 121
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| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet PC87570.PDF ] | |
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