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PC87416 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer PC87416
Beschreibung LPC ServerI/O for Servers and Workstations
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
PC87416 Datasheet, Funktion
July 2003
Revision 1.2
PC87413, PC87414, PC87416, PC87417
LPC ServerI/O for Servers and Workstations
General Description
The National Semiconductor® PC8741x family of LPC Serv-
erI/O devices (“PC8741x”) comprises highly integrated Ad-
vanced I/O products. The PC8741x is targeted for a wide
range of servers and workstations that use the Low Pin Count
(LPC) bus for the host interface and the serial ACCESS.bus
or SMBus® for the embedded controller interface.
The PC8741x features an X-Bus extension for read and write
operations over the X-Bus for both LPC and ACCESS.bus
cycles. Boot Flash and I/O devices can be accessed over this
X-Bus.
Embedded controllers can access the PC8741x and its X-Bus
via the ACCESS.bus or SMBus serial interface when VSB
exists, regardless of the LPC bus state. Some of the
PC8741x logical devices can be disabled, or their pins can be
floated, under control of the VSB-powered serial bus.
The PC8741x provides a VSB-powered high-frequency clock
for on-chip peripherals and for other VSB-powered platform
components.
The PC8741x’s extended wake-up support complements the
chipset’s ACPI controller and the platform embedded control-
lers. The PC8741x can monitor the Power and Sleep buttons
and control the power supply of simple platforms that lack an
embedded controller. The System Wake-Up Control (SWC)
module is powered by VSB and VBAT power supplies. It sup-
ports flexible wake-up and power-off request mechanisms in
any sleep state. It features Main and Standby power-on
elapsed-time counters.
The PC8741x also incorporates a Floppy Disk Controller
(FDC), two serial ports (UARTs), a Keyboard and Mouse
Controller (KBC), a Real-Time Clock (RTC), a fully compliant
IEEE 1284 Parallel Port, General-Purpose Input/Output
(GPIO) for a total of 51 ports and an Interrupt Serializer for
Parallel IRQs.
Outstanding Features
s LPC Interface, based on Intel’s LPC Interface Specifi-
cation, Revision 1.0, September 29th, 1997
s VSB-powered access to modules through ACCESS.bus
or SMBus (PC87413 and PC87417)
s X-Bus Extension for memory and I/O (PC87416 and
PC87417)
s PC01 Revision 0.5 and ACPI Revision 1.0b compliant
s ServerI/O modules: Parallel Port, FDC, two Serial Ports
(UARTs) and a Keyboard and Mouse Controller (KBC)
s Y2K-compliant RTC with 242 bytes of RAM
s 51 GPIO ports with a variety of wake-up events
s Extremely low current consumption in Battery Backup mode
s 128-pin PQFP package
Block Diagram
PC87417(See page 5 for other PC8741x diagrams.)
Serial
Interface
ServerI/O
Clock
Serial
VDD Port 1
Serial
Interface
Serial
Port 2
Parallel Port
Interface
IEEE 1284
Parallel Port
Floppy Drive Keyboard Mouse LPC Serial
Interface Interface Interface Interface IRQ
Floppy Disk
Controller
Keyboard &
Mouse Controller
LPC Bus
Interface
VBAT
VSB
System
Wake-Up Control
Power
On
Timers
RTC
Internal Clocks
Clock
GPIO
Generator Ports
X-Bus
Extension
Device
Configuration
ACCESS.bus
Interface
Wake-Up Power SCI &
Events Control SMI
Low-F High-F I/O X-Bus XIRQ Clock Serial
32.768 KHz Clock Clock Ports Interface
Data
National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. All other
brand or product names are trademarks or registered trademarks of their respective holders.
© 2003 National Semiconductor Corporation
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PC87416 Datasheet, Funktion
Datasheet Revision Record
Revision Date
Status
Comments
July 2000 Preliminary Datasheet First issue - Rev 0.12
October 2000 Preliminary Datasheet Second issue - Rev 0.13
March 2001 Preliminary Datasheet Third issue - Rev 1.0
November 2001 Preliminary Datasheet Fourth issue - Rev 1.1
July 2003 Datasheet
Non-preliminary revision, Rev 1.2
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Revision 1.2

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PC87416 pdf, datenblatt
Table of Contents (Continued)
8.2.11
8.2.12
8.2.13
8.2.14
Power-Up Detection .................................................................................................. 147
Oscillator Activity ....................................................................................................... 147
Interrupt Handling ...................................................................................................... 148
Battery-Backed RAMs and Registers ........................................................................ 148
8.3 RTC REGISTERS .................................................................................................................... 149
8.3.1 RTC Configuration Registers Structure ..................................................................... 149
8.3.2 RTC Runtime Register Map ...................................................................................... 150
8.3.3 Seconds Register (SEC) ........................................................................................... 150
8.3.4 Seconds Alarm Register (SECA) ............................................................................... 151
8.3.5 Minutes Register (MIN) .............................................................................................. 151
8.3.6 Minutes Alarm Register (MINA) ................................................................................. 151
8.3.7 Hours Register (HOR) ............................................................................................... 152
8.3.8 Hours Alarm Register (HORA) .................................................................................. 152
8.3.9 Day-of-Week Register (DOW) ................................................................................... 152
8.3.10 Date-of-Month Register (DOM) ................................................................................. 153
8.3.11 Month Register (MON) .............................................................................................. 153
8.3.12 Year Register (YER) .................................................................................................. 153
8.3.13 RTC Control Register A (CRA) .................................................................................. 154
8.3.14 RTC Control Register B (CRB) .................................................................................. 156
8.3.15 RTC Control Register C (CRC) ................................................................................. 157
8.3.16 RTC Control Register D (CRD) ................................................................................. 157
8.3.17 Date-of-Month Alarm Register (DOMA) ..................................................................... 158
8.3.18 Month Alarm Register (MONA) .................................................................................. 158
8.3.19 Century Register (CEN) ............................................................................................. 158
8.3.20 BCD and Binary Formats ........................................................................................... 159
8.4 USAGE HINTS ........................................................................................................................ 159
8.5 RTC REGISTER BITMAP ........................................................................................................ 160
8.6 RTC GENERAL-PURPOSE RAM MAP ................................................................................... 160
9.0 System Wake-Up Control (SWC)
9.1 OVERVIEW ............................................................................................................................. 161
9.2 FUNCTIONAL DESCRIPTION ................................................................................................ 162
9.2.1 External Events ......................................................................................................... 162
9.2.2 Internal Events ........................................................................................................... 166
9.2.3 Sleep States .............................................................................................................. 167
9.2.4 Interrupt Signals ........................................................................................................ 168
9.2.5 Power Management Signals ...................................................................................... 169
9.2.6 Special Power Management Functions ..................................................................... 172
9.2.7 LED Control ............................................................................................................... 173
9.2.8 Power Active Timers .................................................................................................. 174
9.2.9 Watchdog Function .................................................................................................... 174
9.2.10 Miscellaneous Functions ........................................................................................... 175
9.3 SWC REGISTERS ................................................................................................................... 176
9.3.1 SWC Register Map .................................................................................................... 176
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