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PC87392-VJG Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer PC87392-VJG
Beschreibung 100-Pin LPC SuperI/O Devices for Portable Applications
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
PC87392-VJG Datasheet, Funktion
PRELIMINARY
September 2000
Revision 1.41
PC87391, PC87392, PC87393, PC87393F
100-Pin LPC SuperI/O Devices for Portable Applications
General Description
National Semiconductor’s PC8739x family of LPC SuperI/O
devices is targeted for a wide range of portable applications.
PC99 and ACPI compliant, the PC8739x family features
an X-Bus Extension for read and write operations over the
X-Bus, a full IEEE 1284 Parallel Port with a Parallel Port Mul-
tiplexer (PPM) for external Floppy Disk Drive (FDD) support,
a Musical Instrument Digital Interface (MIDI) port, and a
Game port. Like all National LPC SuperI/O devices, the
PC8739x offers a single-chip solution to the most commonly
used PC I/O peripherals.
The PC8739x family also incorporates: a Floppy Disk Con-
troller (FDC), two enhanced Serial Ports (UARTs), one with
Fast Infrared (FIR, IrDA 1.1 compliant), General-Purpose
Input/Output (GPIO) support for a total of 32 ports, Interrupt
Serializer for Parallel IRQs and an enhanced WATCH-
DOGtimer.
The following features apply to the PC87393F. The feature
lists for other PC8739x devices may differ. See the table on
page 3 for a list of features for each device.
Outstanding Features
q X-Bus Extension for read and write operations
q LPC bus interface, based on Intel’s LPC Interface Spec-
ification Rev. 1.01, February 1999 (supports CLKRUN
and LPCPD signals) and Intel FWH transactions
q PC99 and ACPI compliant
q Serial IRQ support (15 options)
q Interrupt Serializer (four Parallel IRQs to Serial IRQ)
q PPM for external FDD signal support
q MIDI interface compatible with MPU-401 UART mode
q Game port inputs for up to two joysticks
q Protection features, including GPIO lock and pin con-
figuration lock
q 32 GPIO ports (16 standard, 16 with Assert IRQ/SMI)
q 5V tolerant and back-drive protected pins (except LPC
bus pins)
q 100-pin TQFP Package
Block Diagram
PC87393 / PC87393F
Parallel Port\
Floppy Drive Interface
Serial Serial Infrared
Interface Interface Interface
I/O Floppy Drive
Ports Interface
PPM
LPC Serial
Parallel
Interface IRQ SMI IRQs
Serial Port 1
Serial Port 2
with FIR
GPIO Ports
Floppy Disk IEEE 1284
Controller Parallel Port
Bus
Interface
Interrupt
Serializer
VDD Wake-Up
Control
PWUREQ
WATCHDOG
Timer
X-Bus
Extension
Game Port
WDO
X-Bus Interface Game Device
Interface
MIDI Port
MIDI
Interface
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
©2000 National Semiconductor Corporation
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PC87392-VJG Datasheet, Funktion
Table of Contents (Continued)
2.7.2 GPIO Pin Function Lock .............................................................................................. 36
2.8 LPC INTERFACE ...................................................................................................................... 36
2.8.1 LPC Transactions Supported ...................................................................................... 36
2.8.2 CLKRUN Functionality ................................................................................................. 37
2.8.3 LPCPD Functionality ................................................................................................... 37
2.9 REGISTER TYPE ABBREVIATIONS ........................................................................................ 37
2.10 SUPERI/O CONFIGURATION REGISTERS ............................................................................. 37
2.10.1 SuperI/O ID Register (SID) .......................................................................................... 38
2.10.2 SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 38
2.10.3 SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 39
2.10.4 SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 40
2.10.5 SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 41
2.10.6 SuperI/O Configuration 5 Register (SIOCF5) .............................................................. 42
2.10.7 SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 43
2.10.8 SuperI/O Revision ID Register (SRID) ........................................................................ 43
2.10.9 SuperI/O Configuration 8 Register (SIOCF8) .............................................................. 44
2.10.10 SuperI/O Configuration 9 Register (SIOCF9) .............................................................. 45
2.10.11 SuperI/O Configuration A Register (SIOCFA) ............................................................. 46
2.11 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 47
2.11.1 General Description ..................................................................................................... 47
2.11.2 Logical Device 0 (FDC) Configuration ......................................................................... 47
2.11.3 FDC Configuration Register ........................................................................................ 48
2.11.4 Drive ID Register ......................................................................................................... 49
2.12 PARALLEL PORT CONFIGURATION ...................................................................................... 50
2.12.1 General Description ..................................................................................................... 50
2.12.2 Logical Device 1 (PP) Configuration ............................................................................ 51
2.12.3 Parallel Port Configuration Register ............................................................................ 52
2.13 SERIAL PORT 2 CONFIGURATION ......................................................................................... 53
2.13.1 General Description ..................................................................................................... 53
2.13.2 Logical Device 2 (SP2) Configuration .......................................................................... 53
2.13.3 Serial Port 2 Configuration Register ............................................................................ 54
2.14 SERIAL PORT 1 CONFIGURATION ......................................................................................... 55
2.14.1 Logical Device 3 (SP1) Configuration .......................................................................... 55
2.14.2 Serial Port 1 Configuration Register ............................................................................ 55
2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 56
2.15.1 General Description ..................................................................................................... 56
2.15.2 Implementation ............................................................................................................ 56
2.15.3 Logical Device 7 (GPIO) Configuration ....................................................................... 57
2.15.4 GPIO Pin Select Register ............................................................................................ 58
2.15.5 GPIO Pin Configuration Register ................................................................................. 59
2.15.6 GPIO Event Routing Register ...................................................................................... 60
2.16 WATCHDOG TIMER (WDT) CONFIGURATION ...................................................................... 61
2.16.1 Logical Device 10 (WDT) Configuration ...................................................................... 61
2.16.2 WATCHDOG Timer Configuration Register ................................................................ 61
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PC87392-VJG pdf, datenblatt
1.0 Signal/Pin Connection and Description (Continued)
GPIO15/SIN2
GPIO14/RTS2
GPIO13/SOUT2
GPIO12/CTS2
GPIO11/DTR2_BOUT2
GPIO10/RI2
GPIO33
GPIO32
GPIO31/MTR1
GPIO30
GPIO27
GPIO26
VDD
VSS
(XCNF2) NC
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO07
GPIO06
GPIO05
GPIO04
GPIO03
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76 50
77 49
78 48
79 47
80 46
81 45
82 44
83 43
84 42
85 41
86 40
87 39
88 PC87392-VJG 38
89 37
90 36
91 35
92 34
93 33
94 32
95 31
96 30
97 29
98 28
99 27
100 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PD1/TRK0
INIT/DIR
PD2/WP
SLIN_ASTRB/STEP
PD3/RDATA
PD4/DSKCHG
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1
ACK/DR1
BUSY_WAIT/MTR1
VDD
VSS
PE/WDATA
SLCT/WGATE
PNF
DRATE0/IRSL2
DENSEL
INDEX
MTR0
DR0
DIR
STEP
WDATA
WGATE
NC - Not Connected (these pins should be left unconnected)
Thin Quad Flatpack (TQFP), JEDEC
Order Number PC87392-VJG
See NS Package Number VJG100A
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