PC87391-VJG Datasheet PDF - National Semiconductor
| Part Number | PC87391-VJG | |
| Description | 100-Pin LPC SuperI/O Devices for Portable Applications | |
| Manufacturers | National Semiconductor | |
| Logo |  |
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PRELIMINARY
September 2000
Revision 1.41
PC87391, PC87392, PC87393, PC87393F
100-Pin LPC SuperI/O Devices for Portable Applications
General Description
National Semiconductor’s PC8739x family of LPC SuperI/O
devices is targeted for a wide range of portable applications.
PC99 and ACPI compliant, the PC8739x family features
an X-Bus Extension for read and write operations over the
X-Bus, a full IEEE 1284 Parallel Port with a Parallel Port Mul-
tiplexer (PPM) for external Floppy Disk Drive (FDD) support,
a Musical Instrument Digital Interface (MIDI) port, and a
Game port. Like all National LPC SuperI/O devices, the
PC8739x offers a single-chip solution to the most commonly
used PC I/O peripherals.
The PC8739x family also incorporates: a Floppy Disk Con-
troller (FDC), two enhanced Serial Ports (UARTs), one with
Fast Infrared (FIR, IrDA 1.1 compliant), General-Purpose
Input/Output (GPIO) support for a total of 32 ports, Interrupt
Serializer for Parallel IRQs and an enhanced WATCH-
DOG™ timer.
The following features apply to the PC87393F. The feature
lists for other PC8739x devices may differ. See the table on
page 3 for a list of features for each device.
Outstanding Features
q X-Bus Extension for read and write operations
q LPC bus interface, based on Intel’s LPC Interface Spec-
ification Rev. 1.01, February 1999 (supports CLKRUN
and LPCPD signals) and Intel FWH transactions
q PC99 and ACPI compliant
q Serial IRQ support (15 options)
q Interrupt Serializer (four Parallel IRQs to Serial IRQ)
q PPM for external FDD signal support
q MIDI interface compatible with MPU-401 UART mode
q Game port inputs for up to two joysticks
q Protection features, including GPIO lock and pin con-
figuration lock
q 32 GPIO ports (16 standard, 16 with Assert IRQ/SMI)
q 5V tolerant and back-drive protected pins (except LPC
bus pins)
q 100-pin TQFP Package
Block Diagram
PC87393 / PC87393F
Parallel Port\
Floppy Drive Interface
Serial Serial Infrared
Interface Interface Interface
I/O Floppy Drive
Ports Interface
PPM
LPC Serial
Parallel
Interface IRQ SMI IRQs
Serial Port 1
Serial Port 2
with FIR
GPIO Ports
Floppy Disk IEEE 1284
Controller Parallel Port
Bus
Interface
Interrupt
Serializer
VDD Wake-Up
Control
PWUREQ
WATCHDOG
Timer
X-Bus
Extension
Game Port
WDO
X-Bus Interface Game Device
Interface
MIDI Port
MIDI
Interface
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
©2000 National Semiconductor Corporation
www.national.com
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Table of Contents
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAMS ...................................................................................................... 11
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 15
1.3 PIN MULTIPLEXING ................................................................................................................. 15
1.4 PARALLEL PORT MULTIPLEXER (PPM) ................................................................................ 17
1.5 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 18
1.5.1 Bus Interface ............................................................................................................... 18
1.5.2 Clock ............................................................................................................................ 18
1.5.3 Infrared (IR) ................................................................................................................ 18
1.5.4 Floppy Disk Controller (FDC) ..................................................................................... 19
1.5.5 Game Port (PC87393 and PC87393F) ....................................................................... 20
1.5.6 General-Purpose Input/Output (GPIO) Ports (PC87392, PC87393 and PC87393F) 20
1.5.7 Musical Instrument Digital Interface (MIDI) Port (PC87393 and PC87393F) ............ 20
1.5.8 Parallel Port ................................................................................................................ 21
1.5.9 Power and Ground ..................................................................................................... 21
1.5.10 Serial Port 1 and Serial Port 2 (SP1 and SP2) ............................................................ 22
1.5.11 Strap Configuration ...................................................................................................... 23
1.5.12 Wake-Up Control ......................................................................................................... 23
1.5.13 WATCHDOG Timer ..................................................................................................... 23
1.5.14 X-Bus Extension (PC87393 and PC87393F) ............................................................. 23
1.6 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 24
2.0 Device Architecture and Configuration
2.1 OVERVIEW ............................................................................................................................... 26
2.2 CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 26
2.2.1 The Index-Data Register Pair ...................................................................................... 26
2.2.2 Banked Logical Device Registers Structure ................................................................ 28
2.2.3 Standard Logical Device Configuration Register Definitions ....................................... 29
2.2.4 Standard Configuration Registers ............................................................................... 31
2.2.5 Default Configuration Setup ........................................................................................ 32
2.2.6 Power States ............................................................................................................... 32
2.2.7 Address Decoding ....................................................................................................... 32
2.3 THE CLOCK MULTIPLIER ........................................................................................................ 33
2.3.1 Functionality ................................................................................................................ 33
2.3.2 Chip Power-Up ............................................................................................................ 33
2.3.3 Disabling the Clock ...................................................................................................... 33
2.3.4 Specifications .............................................................................................................. 33
2.4 INTERRUPT SERIALIZER ........................................................................................................ 34
2.5 WAKE-UP CONTROL ............................................................................................................... 34
2.6 THE PARALLEL PORT MULTIPLEXER (PPM) ........................................................................ 34
2.6.1 PPM Power Save Mode .............................................................................................. 35
2.7 PROTECTION ........................................................................................................................... 36
2.7.1 Pin Configuration Lock ................................................................................................ 36
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