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PDF PC87373 Data sheet ( Hoja de datos )
| Número de pieza | PC87373 | |
| Descripción | LPC SuperI/O with Glue Functions | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Preliminary
October 2002
Revision 1.1
PC87373
LPC SuperI/O with Glue Functions
General Description
The National Semiconductor® PC87373 Advanced I/O prod-
uct is a member of the PC8737x SuperI/O family. All
PC8737x devices are highly integrated and are pin and soft-
ware compatible, thus providing drop-in interchangeability
and enabling a variety of assembly options using only a sin-
gle motherboard and BIOS.
PC87373 integration allows for a smaller system board size and
saves on total system cost.
The PC87373 includes legacy SuperI/O functions, system
glue functions, fan monitoring and control, commonly used
functions such as GPIO, and ACPI-compliant Power Man-
agement support.
The PC87373 integrates miscellaneous analog and digital
system glue functions to reduce the number of discrete
components required. The host communicates with the
functions integrated in the PC87373 device through an LPC
Bus Interface.
The PC87373 Legacy functions are: two serial ports, a fully
compliant IEEE 1284 Parallel Port, a Floppy Disk Controller
(FDC), a Keyboard/Mouse Controller (KBC), a Game Port
and a MIDI Port.
The Fan Speed Control and Monitor (FSCM) module allows
the system to monitor and control three fans.
The PC87373 extended wake-up support complements the
ACPI controller in the chipset. The System Wake-Up Control
(SWC) module, powered by VSB3, supports a flexible wake-
up mechanism.
There are 13 General-Purpose Input/Output (GPIO) ports;
these allow system control and wake-up on system events.
Outstanding Features
s Legacy modules: Parallel Port, Floppy Disk Controller
(FDC), two Serial Ports, Keyboard and Mouse Control-
ler (KBC), Game Port and MIDI Port
s Glue functions to complement the South Bridge func-
tionality
s Fan Speed monitoring and control of three fans
s VSB3-powered Power Management with 20 wake-up
sources
s Controls three LED indicators
s 13 GPIO ports with a variety of wake-up options
s LPC interface, based on Intel’s LPC Interface Specifica-
tion Revision 1.0, September 29th, 1997
s PC01 Revision 1.0 and Advanced Configuration and Pow-
er Interface (ACPI) Specification Revision 2.0 compliant
s 128-pin PQFP package
Block Diagram
14.31818
MHzInMteIrDfaIce
Joystick
Interface
Serial
Interface
Serial
Interface
Parallel
Port
Interface
Floppy
Drive PS/2 KBC LPC Serial
Interface Interfaces Ports Interface IRQ
Clock MIDI
Generator Port
48 MHz
Game
Port
Serial
Port 1
Serial
Port 2
IEEE 1284 Floppy
Parallel
Disk
Port
Controller
Keyboard
& Mouse
Controller
Internal Bus
LPC Bus
Interface
VDD3
Fan Speed
Control and
Monitor
Glue
Functions
System
Wake-Up
Control
GPIO Ports
Tachometer PWM
Inputs Outputs
Miscellaneous
Wake-Up PME
I/O VBAT Events LEDs
I/O
Ports
PnP
Configuration
Registers
VSB3
32.768 KHz
National Semiconductor is a registered trademark of National Semiconductor Corporation. All other brand or product names are trademarks or registered trade-
marks of their respective holders.
© 2002 National Semiconductor Corporation
www.national.com
1 page  
Datasheet Revision Record
Revision Date
Status
Comments
August 2002 Preliminary Datasheet First issue - Revision 1.0
October 2002 Preliminary Datasheet Second issue - Revision 1.1
Revision 1.1
5 www.national.com
5 Page 
Table of Contents (Continued)
11.2.5
11.2.6
11.2.7
11.2.8
11.2.9
MIDI Signals Routing Control Logic ........................................................................... 132
Operation Modes ....................................................................................................... 132
MIDI Port Status Flags .............................................................................................. 133
MIDI Port Interrupts ................................................................................................... 134
Enhanced MIDI Port Features ................................................................................... 134
11.3 MIDI PORT REGISTERS ........................................................................................................ 136
11.3.1 MIDI Port Register Map ............................................................................................. 136
11.3.2 MIDI Data In Register (MDI) ...................................................................................... 136
11.3.3 MIDI Data Out Register (MDO) ................................................................................. 136
11.3.4 MIDI Status Register (MSTAT) .................................................................................. 137
11.3.5 MIDI Command Register (MCOM) ............................................................................ 138
11.3.6 MIDI Control Register (MCNTL) ................................................................................ 138
11.4 MIDI PORT BITMAP .............................................................................................................. 139
12.0 Legacy Functional Blocks
12.1 FLOPPY DISK CONTROLLER (FDC) ..................................................................................... 140
12.1.1 General Description ................................................................................................... 140
12.1.2 FDC Bitmap Summary ............................................................................................... 141
12.2 PARALLEL PORT .................................................................................................................... 142
12.2.1 General Description ................................................................................................... 142
12.2.2 Parallel Port Register Map ......................................................................................... 142
12.2.3 Parallel Port Bitmap Summary .................................................................................. 143
12.3 UART FUNCTIONALITY (SERIAL PORT 1 AND SERIAL PORT 2) ....................................... 145
12.3.1 General Description ................................................................................................... 145
12.3.2 UART Register Bank Overview ................................................................................. 145
12.3.3 SP1 and SP2 Register Maps .................................................................................... 145
12.3.4 SP1 and SP2 Bitmap Summary ............................................................................... 147
12.4 KEYBOARD AND MOUSE CONTROLLER (KBC) .................................................................. 149
12.4.1 General Description ................................................................................................... 149
12.4.2 KBC Register Map ..................................................................................................... 150
12.4.3 KBC Bitmap Summary ............................................................................................... 150
13.0 Device Characteristics
13.1 GENERAL DC ELECTRICAL CHARACTERISTICS ............................................................... 151
13.1.1 Recommended Operating Conditions ....................................................................... 151
13.1.2 Absolute Maximum Ratings ....................................................................................... 151
13.1.3 Capacitance .............................................................................................................. 151
13.1.4 Power Consumption under Recommended Operating Conditions ............................ 152
13.1.5 Voltage Thresholds .................................................................................................... 152
13.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES ................................................ 153
13.2.1 Input, Game Port Compatible with Schmitt Trigger ................................................... 153
13.2.2 Input, TTL Compatible ............................................................................................... 153
13.2.3 Input, TTL Compatible, with Schmitt Trigger ............................................................. 153
13.2.4 Input, TTL Compatible, with 400 mV Schmitt Trigger ................................................ 154
13.2.5 Input, PCI 3.3V Compatible ....................................................................................... 154
13.2.6 Analog Input .............................................................................................................. 154
Revision 1.1
11 www.national.com
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