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PDF PC87372 Data sheet ( Hoja de datos )
| Número de pieza | PC87372 | |
| Descripción | LPC SuperI/O with Glue Functions | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 2002
Revision 1.2
PC87372
LPC SuperI/O with Glue Functions
General Description
The National Semiconductor® PC87372 Advanced I/O prod-
uct is a member of the PC8737x SuperI/O family. All
PC8737x devices are highly integrated and are pin and soft-
ware compatible, thus providing drop-in interchangeability
and enabling a variety of assembly options using only a sin-
gle motherboard and BIOS.
PC87372 integration allows for a smaller system board size and
saves on total system cost.
The PC87372 includes legacy SuperI/O functions, system
glue functions, fan monitoring and control, commonly used
functions such as GPIO, and ACPI-compliant Power Man-
agement support.
The PC87372 integrates miscellaneous analog and digital
system glue functions to reduce the number of discrete
components required. The host communicates with the
functions integrated in the PC87372 device through an LPC
Bus Interface.
The PC87372 Legacy functions are: a serial port (UART), a
fully compliant IEEE 1284 Parallel Port, a Floppy Disk Con-
troller (FDC) and a Keyboard/Mouse Controller (KBC).
The Fan Speed Monitor (FSM) module allows the system to
monitor two fans.
The PC87372 extended wake-up support complements the
ACPI controller in the chipset. The System Wake-Up Control
(SWC) module, powered by VSB3, supports a flexible wake-
up mechanism.
There are 13 General-Purpose Input/Output (GPIO) ports;
these allow system control and wake-up on system events.
Outstanding Features
s Legacy modules: Parallel Port, Floppy Disk Controller
(FDC), Serial Port and a Keyboard and Mouse Control-
ler (KBC)
s Glue functions to complement the South Bridge func-
tionality
s Fan Speed monitoring of two fans
s VSB3-powered Power Management with 20 wake-up
sources
s Controls three LED indicators
s 13 GPIO ports with a variety of wake-up options
s LPC interface, based on Intel’s LPC Interface Specifica-
tion Revision 1.0, September 29th, 1997
s PC01 Revision 1.0 and Advanced Configuration and Pow-
er Interface (ACPI) Specification Revision 2.0 compliant
s 128-pin PQFP package
Block Diagram
14.31818 MHz
Serial
Interface
Parallel Port Floppy Drive Keyboard Mouse
LPC Serial
Interface
Interface Interface Interface Interface IRQ
Clock
Generator
Serial Port
48 MHz
IEEE 1284
Parallel Port
Floppy Disk
Keyboard &
Controller Mouse Controller
Internal Bus
LPC Bus
Interface
VDD3
Fan Speed
Monitor
Tachometer
Inputs
Glue
Functions
System
Wake-Up Control GPIO Ports
Miscellaneous Wake-Up PME
I/O Events
I/O
Ports
PnP
Configuration
Registers
VSB3
32.768 KHz
National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. All other brand or product names are trademarks
or registered trademarks of their respective holders.
© 2002 National Semiconductor Corporation
www.national.com
1 page  
Table of Contents
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAMS ................................................................................................ 11
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 12
1.3 PIN MULTIPLEXING ................................................................................................................. 13
1.4 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 14
1.4.1 LPC Interface .............................................................................................................. 14
1.4.2 Serial Port (UART) .................................................................................................. 15
1.4.3 Parallel Port .............................................................................................................. 16
1.4.4 Floppy Disk Controller (FDC) .................................................................................... 17
1.4.5 Keyboard and Mouse Controller (KBC) ..................................................................... 18
1.4.6 General-Purpose I/O (GPIO) ...................................................................................... 18
1.4.7 Fan Speed Monitor (FSM) ......................................................................................... 18
1.4.8 System Wake-Up Control (SWC) .............................................................................. 19
1.4.9 Clocks ..................................................................................................................... 19
1.4.10 Glue Functions ........................................................................................................... 20
1.4.11 Configuration Straps and Testing ............................................................................... 21
1.4.12 Power and Ground .................................................................................................... 22
1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 22
2.0 Power, Reset and Clocks
2.1 POWER ..................................................................................................................................... 24
2.1.1 Power Planes .............................................................................................................. 24
2.1.2 Power States ............................................................................................................... 24
2.1.3 Power Connection and Layout Guidelines .................................................................. 25
2.2 RESET SOURCES AND TYPES ............................................................................................... 26
2.2.1 VSB Power-Up Reset .................................................................................................. 26
2.2.2 VDD Power-Up Reset .................................................................................................. 27
2.2.3 Hardware Reset ........................................................................................................... 27
2.2.4 Software Reset ............................................................................................................ 27
2.3 CLOCK DOMAINS ..................................................................................................................... 27
2.3.1 LPC Domain ................................................................................................................ 27
2.3.2 48 MHz Domain ........................................................................................................... 28
2.3.3 32 KHz Domain ........................................................................................................... 28
2.4 TESTABILITY SUPPORT .......................................................................................................... 28
2.4.1 ICT ............................................................................................................................... 28
2.4.2 XOR Tree Testing ........................................................................................................ 29
3.0 Device Architecture and Configuration
3.1 OVERVIEW ............................................................................................................................... 30
3.2 CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 30
3.2.1 The Index-Data Register Pair ...................................................................................... 30
3.2.2 Banked Logical Device Registers Structure ................................................................ 31
3.2.3 Standard Configuration Register Definitions ............................................................... 32
3.2.4 Standard Configuration Registers ............................................................................ 34
3.2.5 Default Configuration Setup ........................................................................................ 35
Revision 1.2
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5 Page 
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAMS
CLOCKI14
HD_LED
PRIMARY_HD
SECONDARY_HD
SCSI
REF5V
VSB5
REF5V_STBY
PCIRST_OUT
PCIRST_OUT2
FPRST
VSB3
BKFD_CUT
VSS
LATCHED_BF_CUT
SCK_BJT_GATE
PS_ON
PWRGD_PS
CPU_PRESENT
PWRGD_3V
SLP_S3
SLP_S5
SMB1_SCL
SMB2_SCL
SMB1_SDA
SMB2_SDA
CLOCKI32
RSMRST
VSB3
GRN_LED
YLW_LED
VSS
VCORF
N.C.
SIOPME
AUD_LINK_RST
CDC_DWN_ENAB/GPIO14
CDC_DWN_RST
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
PC87372
128-Pin PQFP
PC87372-xxx/VLA
(Top View)
38 PD6
37 PD7
36 ACK
35 BUSY_WAIT
34 PE
33 SLCT
32 RI
31 VDD3
30 DTR_BOUT/XOR_OUT/BADDR
29 VSS
28 CTS
27 SOUT/TEST
26 RTS/TRIS
25 SIN
24 DSR
23 DCD
22 DENSEL
21 DRATE0
20 INDEX
19 MTR0
18 DR0
17 DIR
16 STEP
15 WDATA
14 WGATE
13 TRK0
12 WP
11 RDATA
10 HDSEL
9 DSKCHG
8 VSS
7 KBRST
6 VDD3
5 GA20
4 KBDAT
3 KBCLK
2 MDAT
1 MCLK
Plastic Quad Flatpack (PQFP), JEDEC
Order Number PC87372-xxx/VLA
See NS Package Number VLA128A
N.C. = Not Connected
xxx = Three-character identifier for National data, and keyboard ROM and/or customer identification code
Revision 1.2
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PC87372.PDF ] | |
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