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PC87365 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer PC87365
Beschreibung 128-Pin LPC SuperI/O with System Hardware Monitoring
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
PC87365 Datasheet, Funktion
PRELIMINARY
November 2000
Revision 2.01
PC87365
128-Pin LPC SuperI/O with System Hardware Monitoring
General Description
The PC87365, a member of National Semiconductor’s 128-
pin LPC SuperI/O family, features National’s new System
Hardware Monitoring capability. The PC87365 is PC99 and
ACPI compliant, and offers a single-chip solution to the most
commonly used PC I/O peripherals.
System Hardware Monitoring provides minimum power con-
sumption and maximum operating efficiency within the system
environment. It integrates National’s Voltage Level Monitor
(VLM) which monitors system voltages using 8-bit Analog to
Digital (A/D) conversion, seven analog input channels and
VREF input, and National’s diode input Temperature Sensor
for full, PC system thermal control.
The PC87365 also incorporates: Fan Speed Control and
Monitor (FSCM) for three fans, extended wake-up support
for a wide range of wake-up events, system design protection
features, a Floppy Disk Controller (FDC), a Keyboard and
Mouse Controller (KBC), ACCESS.bus® Interface (ACB),
System Wake-Up Control (SWC), General-Purpose In-
put/Output (GPIO) support for 40 ports, Interrupt Serializer
for Parallel IRQs, an enhanced WATCHDOG Timer (WDT),
a full IEEE 1284 Parallel Port and two enhanced Serial Ports
(UARTs), one with Infrared (IR) support.
Outstanding Features
q System Hardware Monitoring including:
Diode-based Temperature Sensor (TMS)
Voltage Level Monitor (VLM) with VID inputs
q Extended Wake-Up support, including legacy/ACPI
power button support, direct power supply control in
response to wake-up events, power-fail recovery
q Protection features, including I/O access lock, chassis
hood lock/unlock, chassis intrusion detection, GPIO lock
and pin configuration lock
q Fan Speed Control and Monitor for three fans
q Serial IRQ support (15 options)
q Interrupt Serializer (11 Parallel IRQs to Serial IRQ)
q Bus interface, based on Intel’s LPC Interface Specifi-
cation Revision 1.0, September 29th, 1997
q ACCESS.bus Interface, SMbus® physical layer compatible
q 40 GPIO Ports (29 standard, including 15 with Assert
IRQ/SMI/PWUREQs interrupts; 11 VSB powered)
q Blinking LEDs
q 128-pin PQFP Package
Block Diagram
Serial
Serial Infrared
Interface Interface Interface
I/O
Ports
Floppy Drive Parallel Port LPC Serial Analog
Diode
Interface
Interface Interface IRQ SMI Inputs VREF Interface
Serial Port 1
Serial Port 2
with IR
GPIO Ports
Floppy Disk IEEE 1284
Controller Parallel Port
Bus
Interface
System
Hardware
Monitoring
AV DD
VDD
VBdAT
VSB
System Wake-Up ACCESS.bus
Control
Interface
Power Wake-Up PWUREQ SCL SDA
Control Events
WATCHDOG
Fan Speed
Keyboard &
Timer
Control & Monitor Mouse Controller
WDO
3 Control 3 Monitor Keyboard & Ports
Outputs Inputs Mouse I/F
Interrupt
Serializer
Parallel
IRQs
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
© 2000 National Semiconductor Corporation
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PC87365 Datasheet, Funktion
Table of Contents (Continued)
2.5 POWER SUPPLY CONTROL (PSC) ......................................................................................... 40
2.6 LED OPERATION AND STATES .............................................................................................. 43
2.7 POWER SUPPLY CONTROL AND LED CONFIGURATION .................................................... 43
2.8 REGISTER TYPE ABBREVIATIONS ........................................................................................ 43
2.9 SUPERI/O CONFIGURATION REGISTERS ............................................................................. 44
2.9.1 SuperI/O ID Register (SID) .......................................................................................... 45
2.9.2 SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 45
2.9.3 SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 46
2.9.4 SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 47
2.9.5 SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 48
2.9.6 SuperI/O Configuration 5 Register (SIOCF5) .............................................................. 49
2.9.7 SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 50
2.9.8 SuperI/O Revision ID Register (SRID) ........................................................................ 50
2.9.9 SuperI/O Configuration 8 Register (SIOCF8) .............................................................. 51
2.9.10 SuperI/O Configuration A Register (SIOCFA) ............................................................. 52
2.9.11 SuperI/O Configuration B Register (SIOCFB) ............................................................. 53
2.9.12 SuperI/O Configuration C Register (SIOCFC) ............................................................. 54
2.9.13 SuperI/O Configuration D Register (SIOCFD) ............................................................. 55
2.10 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 56
2.10.1 General Description ..................................................................................................... 56
2.10.2 Logical Device 0 (FDC) Configuration ......................................................................... 56
2.10.3 FDC Configuration Register ........................................................................................ 57
2.10.4 Drive ID Register ......................................................................................................... 58
2.11 PARALLEL PORT CONFIGURATION ...................................................................................... 59
2.11.1 General Description ..................................................................................................... 59
2.11.2 Logical Device 1 (PP) Configuration ............................................................................ 60
2.11.3 Parallel Port Configuration Register ............................................................................ 61
2.12 SERIAL PORT 2 CONFIGURATION ......................................................................................... 62
2.12.1 General Description ..................................................................................................... 62
2.12.2 Logical Device 2 (SP2) Configuration .......................................................................... 62
2.12.3 Serial Port 2 Configuration Register ............................................................................ 62
2.13 SERIAL PORT 1 CONFIGURATION ......................................................................................... 63
2.13.1 Logical Device 3 (SP1) Configuration .......................................................................... 63
2.13.2 Serial Port 1 Configuration Register ............................................................................ 63
2.14 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION ..................................................... 64
2.14.1 Logical Device 4 (SWC) Configuration ........................................................................ 64
2.15 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION ..................................... 65
2.15.1 General Description ..................................................................................................... 65
2.15.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration .................................. 66
2.15.3 KBC Configuration Register ........................................................................................ 67
2.16 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 68
2.16.1 General Description ..................................................................................................... 68
2.16.2 Implementation ............................................................................................................ 68
2.16.3 Logical Device 7 (GPIO) Configuration ....................................................................... 69
2.16.4 GPIO Pin Select Register ............................................................................................ 70
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PC87365 pdf, datenblatt
Table of Contents (Continued)
11.4.4 SP1 and SP2 Bitmap Summary for UART Functionality ........................................... 193
11.5 IR FUNCTIONALITY (SP2) ..................................................................................................... 195
11.5.1 General Description ................................................................................................... 195
11.5.2 IR Mode Register Bank Overview ............................................................................. 195
11.5.3 SP2 Register Map for IR Functionality ...................................................................... 196
11.5.4 SP2 Bitmap Summary for IR Functionality ................................................................ 197
12.0 Device Characteristics
12.1 GENERAL DC ELECTRICAL CHARACTERISTICS ............................................................... 199
12.1.1 Recommended Operating Conditions ....................................................................... 199
12.1.2 Absolute Maximum Ratings ....................................................................................... 199
12.1.3 Capacitance .............................................................................................................. 199
12.1.4 Power Consumption under Recommended Operating Conditions ............................ 200
12.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES ................................................ 200
12.2.1 Input, CMOS Compatible ........................................................................................... 200
12.2.2 Input, PCI 3.3V .......................................................................................................... 200
12.2.3 Input, SMBus Compatible .......................................................................................... 200
12.2.4 Input, Strap Pin .......................................................................................................... 201
12.2.5 Input, TTL Compatible ............................................................................................... 201
12.2.6 Input, TTL Compatible with Schmitt Trigger .............................................................. 201
12.2.7 Output, PCI 3.3V ....................................................................................................... 202
12.2.8 Output, Totem-Pole Buffer ......................................................................................... 202
12.2.9 Output, Open-Drain Buffer ......................................................................................... 202
12.2.10 Input, Analog ............................................................................................................. 202
12.2.11 Input, Analog ............................................................................................................. 202
12.2.12 Input, Analog ............................................................................................................. 203
12.2.13 Output, Analog ........................................................................................................... 203
12.2.14 Output, Analog ........................................................................................................... 203
12.2.15 Exceptions ................................................................................................................. 203
12.3 INTERNAL RESISTORS ......................................................................................................... 204
12.3.1 Pull-Up Resistor ......................................................................................................... 204
12.3.2 Pull-Down Resistor .................................................................................................... 204
12.4 ANALOG CHARACTERISTICS ............................................................................................... 204
12.4.1 VLM ........................................................................................................................... 204
12.4.2 TMS ........................................................................................................................... 205
12.5 AC ELECTRICAL CHARACTERISTICS .................................................................................. 206
12.5.1 AC Test Conditions .................................................................................................... 206
12.5.2 Clock Timing .............................................................................................................. 206
12.5.3 LCLK and LRESET .................................................................................................... 207
12.5.4 LPC and SERIRQ Signals ......................................................................................... 208
12.5.5 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing ........................... 209
12.5.6 Modem Control Timing .............................................................................................. 210
12.5.7 FDC Write Data Timing ............................................................................................. 210
12.5.8 FDC Drive Control Timing ......................................................................................... 211
12.5.9 FDC Read Data Timing ............................................................................................. 211
12.5.10 Standard Parallel Port Timing .................................................................................... 212
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