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PDF PC87334VJG Data sheet ( Hoja de datos )
| Número de pieza | PC87334VJG | |
| Descripción | SuperI/O 3.3V/5V Floppy Disk Controller/ Dual UARTs/ Infrared/ IEEE1284 Parallel Port/ and IDE Interface | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
March 1995
PC87334VLJ PC87334VJG SuperI OTM
3 3V 5V Floppy Disk Controller Dual UARTs Infrared
IEEE1284 Parallel Port and IDE Interface
General Description
The PC87334VLJ PC87334VJG is a single chip solution for
most commonly used I O peripherals in ISA EISA and Mi-
croChannel based computers It incorporates a Floppy
Disk Controller (FDC) two full featured UARTs an IEEE
1284 compatible parallel port and all the necessary control
logic for an IDE interface Standard PC-AT address decod-
ing for all the peripherals and a set of configuration registers
are also implemented in this highly integrated member of
the SuperI O family Advanced power management fea-
tures mixed voltage operation and integrated Serial-Infra-
Red (SIR) support makes the PC87334 an ideal choice for
low-power and or portable personal computer applications
The PC87334 FDC uses a high performance digital data
separator eliminating the need for any external filter compo-
nents It is fully compatible with the PC8477 and incorpo-
rates a superset of DP8473 NEC mPD765 and N82077 flop-
py disk controller functions All popular 5 25 and 3 5 flop-
py drives including the 2 88 MB 3 5 floppy drive are sup-
ported In addition automatic media sense and 2 Mbps tape
drive support are provided by the FDC
The two UARTs are fully NS16450 and NS16550 compati-
ble Both ports support MIDI baud rates and one port also
supports IrDA and the HP SIR compliant signaling protocol
The parallel port is fully IEEE 1284 level 2 compatible The
SPP (Standard Parallel Port) is fully compatible with ISA
EISA and MicroChannel parallel ports In addition to the
SPP EPP (Enhanced Parallel Port) and ECP (Extended Ca-
pabilities Port) modes are supported by the parallel port
All IDE control signals with DMA support are provided by the
PC87334 Only external signal buffers are required to imple-
ment a complete IDE interface
(Continued)
Features
Y 100% compatible with ISA EISA and MicroChannel
architectures
Y The Floppy Disk Controller
Software compatible with the DP8473 the 765A and
the N82077
16-byte FIFO (disabled by default)
Burst and Non-Burst modes
Perpendicular Recording drive support
New high-performance internal digital data separator
(no external filter components required)
Low-power CMOS with enhanced power-down mode
Automatic media-sense support with full IBM TDR
(Tape Drive Register) implementation
Supports fast 2 Mbps and standard 1 Mbps
500 kbps 250 kbps tape drives
Y The Bidirectional Parallel Port
Enhanced Parallel Port (EPP) compatible
Extended Capabilities Port (ECP) compatible includ-
ing level 2 support
Bidirectional under either software or hardware
control
Compatible with ISA EISA and MicroChannel
architectures
Ability to multiplex FDC signals on parallel port pins
allows use of an external Floppy Disk Drive (FDD)
Includes protection circuit to prevent damage to the
parallel port when a connected printer is powered up
or is operated at a higher voltage
(Continued)
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
SuperI OTM is a trademark of National Semiconductor Corporation
IBM MicroChannel PC-AT and PS 2 are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation TL C 12039
TL C 12039 – 1
RRD-B30M65 Printed in U S A
1 page  
FIGURE 2-1
FIGURE 2-2
FIGURE 3-1
FIGURE 4-1
FIGURE 4-2
FIGURE 5-1
FIGURE 5-2
FIGURE 5-3
FIGURE 6-1
FIGURE 6-2
FIGURE 7-1
FIGURE 7-2
FIGURE 7-3
FIGURE 7-4
FIGURE 7-5
FIGURE 7-6
FIGURE 7-7
FIGURE 8-1
FIGURE 10-1
FIGURE 10-2
FIGURE 10-3
FIGURE 10-4
FIGURE 10-5
FIGURE 10-6a
FIGURE 10-6b
FIGURE 10-6c
FIGURE 10-7
FIGURE 10-8
FIGURE 10-9
FIGURE 10-10
FIGURE 10-11
FIGURE 10-12
FIGURE 10-13
FIGURE 10-14
FIGURE 10-15
FIGURE 10-16
FIGURE 10-17
FIGURE 10-18
FIGURE 10-19
FIGURE 10-20
List of Figures
PC87334 Configuration Registers
PC87334 Four Floppy Drive Circuit Example
FDC Functional Block Diagram
FDC Command Structure
IBM Perpendicular and ISO Formats Supported by the Format Command
PC87334 Dynamic Window Margin Performance
Read Data Algorithm State Diagram
Perpendicular Recording Drive R W Head and Pre-Erase Head
PC87334 Composite Serial Data
Reciever FIFO Trigger Level
EPP 1 7 Address Write
EPP 1 7 Address Read
EPP Write with ZWS
EPP 1 9 Address Write
EPP 1 9 Address Read
ECP (Forward) Write Cycle
ECP (Backward) Read Cycle
IDE Interface Signal Equations (Non-DMA)
Clock Timing
Microprocessor Read Timing
Microprocessor Write Timing
Baud Out Timing
Transmitter Timing
Receiver Timing
Mode Receiver Timing
Timeout Receiver Timing
MODEM Control Timing
DMA Timing
Reset Timing
Write Data Timing
Drive Control Timing
Read Data Timing
IDE Timing
Compatible Mode Parallel Port Interrupt Timing
Extended Mode Parallel Port Interrupt Timing
Typical Parallel Port Data Exchange
Enhanced Parallel Port Timing
ECP Parallel Port Forward Timing Diagram
ECP Parallel Port Backward Timing Diagram
3F3 Read Timing
5
5 Page 
1 0 Pin Description (Continued)
Symbol
PQFP TQFP I O
Pin Pin
Function
DCD1 2
77 69 75 67 I Data Carrier Detect When low this signal indicates that the MODEM or data set has
detected the data carrier The DCD signal is a MODEM status input whose condition the CPU
can test by reading bit 7 (DCD) of the MODEM Status Register (MSR) for the appropriate
serial channel Bit 7 is the complement of the DCD signal Bit 3 (DDCD) of the MSR indicates
whether the DCD input has changed state since the previous reading of the MSR
Note Whenever the DDCD bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled
DENSEL
Normal
Mode
48
46 O Density Select Indicates that a high FDC density data rate (500 kbps 1 Mbps or 2 Mbps) or
a low density data rate (250 kbps or 300 kbps) is selected DENSEL is active high for high
density (5 25 drives) when IDENT is high and active low for high density (3 5 drives) when
IDENT is low DENSEL is also programmable via the Mode command (see Section 4 2 6)
DENSEL
PPM
78 76 O Density Select This pin provides an additional Density Select signal in PPM Mode when
Mode
PNF e 0 (See AFD and Table 7-5 for further information )
DIR
Normal
Mode
41
39 O Direction This output determines the direction of the floppy disk drive (FDD) head
movement (active e step in inactive e step out) during a seek operation During reads or
writes DIR is inactive
DIR
PPM
Mode
80 78 O Direction This pin provides an additional direction signal in PPM Mode when PNF e 0 (See
INIT and Table 7-5 for further information )
DR0 1
Normal 44 45 42 43 O Drive SeIect 0 1 These are the decoded Drive Select outputs that are controlled by the
Mode
Digital Output Register bits D0 D1 The Drive Select outputs are gated with DOR bits 4 – 7
These are active low outputs They are encoded with information to control four FDDs when
bit 4 of the Function Enable Register (FER) is set (See MTR0 1 for more information ) DR0
exchanges logical drive values with DR1 when bit 4 of Function Control Register (FCR) is set
(See Table 7-5 for further information )
DR1
PPM
Mode
85 83 O Drive Select 1 This pin provides an additional Drive Select signal in PPM Mode when PNF
e 0 It is drive select 1 when bit 4 of FCR is 0 It is drive select 0 when bit 4 of FCR is 1 This
signal is active low (See ACK and Table 7-5 for further information )
DRATE0 1
Normal 52 51 50 49 O Data Rate 0 1 These outputs reflect the currently selected FDC data rate (bits 0 and 1 in the
Mode
Configuration Control Register (CCR) or the Data Rate Select Register (DSR) whichever was
written to last) The pins are totem-pole buffered outputs (6 mA sink 6 mA source)
DRATE0
PPM
87 85 O Data Rate 0 This pin provides an additional Data Rate signal in PPM mode when PNF e 0
Mode
(See PD6 and Table 7-5 for further information )
DRID0 1
59 56 54 54 I Drive ID These pins accept input from the floppy disk drive which indicates the type of drive
in use These pins should be tied low if they are not used DRID1 is configured when bit 2 of
ASC is 1 and bit 1 of ASC is 0 (See IOCS16 IDEACK IDEHI VLD0 3F3RD IRTX and IRRX
for further information )
DRV2
49 47 I Drive2 This input indicates whether a second floppy disk drive has been installed The state
of this pin is available from Status Register A in PS 2 mode (See PNF for further
information )
DR23
49 47 I Drive 2 or 3 DR23 is asserted when either Drive 2 or Drive 3 is accessed (except during
logical drive exchange see bit 3 of TDR) This pin is configured when bit 1 of ASC is 0 (See
DRV2 and PNF for further information )
11
11 Page | ||
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| PDF Descargar | [ Datasheet PC87334VJG.PDF ] | |
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