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PDF PC87332 Data sheet ( Hoja de datos )
| Número de pieza | PC87332 | |
| Descripción | PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller/ Dual UARTs/ IEEE1284 Parallel Port/ and IDE Interfac | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
May 1995
PC87332VLJ (3 3V 5V) and PC87332VLJ-5 (5V)
(SuperI OTM III Premium Green)
Floppy Disk Controller Dual UARTs IEEE1284
Parallel Port and IDE Interface
General Description
The PC87332VLJ and PC87332VLJ-5 are single chip solu-
tions for most commonly used I O peripherals in ISA EISA
and MicroChannel based computers It incorporates a
Floppy Disk Controller (FDC) two full featured UARTs an
IEEE 1284 compatible parallel port and all the necessary
control logic for an IDE interface Standard PC-AT address
decoding for all the peripherals and a set of configuration
registers are also implemented in this highly integrated
member of the SuperI O family Advanced power manage-
ment features and mixed voltage operation in the VLJ ver-
sion make the PC87332 chips an ideal for low-power and or
portable personal computer applications
The PC87332 FDC uses a high performance digital data
separator eliminating the need for any external filter compo-
nents It is fully compatible with the PC8477 and incorpo-
rates a superset of DP8473 NEC mPD765 and N82077 flop-
py disk controller functions All popular 5 25 and 3 5 flop-
py drives including the 2 88 MB 3 5 floppy drive are sup-
ported In addition automatic media sense and 2 Mbps tape
drive support are provided by the FDC
The two UARTs are fully NS16450 and NS16550 compati-
ble Both ports support MIDI baud rates
(Continued)
Features
Y Floppy Disk Controller
Software compatible with the DP8473 the 765A and
the N82077
16-byte FIFO (disabled by default)
Burst and Non-Burst modes
Perpendicular Recording drive support
New high-performance internal digital data separator
(no external filter components required)
Low-power CMOS with enhanced power-down mode
Automatic media-sense support
Supports fast 2 Mbps and standard 1 Mbps
500 kbps 250 kbps tape drives
Y Bidirectional Parallel Port
Enhanced Parallel Port (EPP) compatible
Extended Capabilities Port (ECP) compatible includ-
ing level 2 support
Bidirectional under either software or hardware
control
Ability to multiplex FDC signals on parallel port pins
allows use of an external Floppy Disk Drive (FDD)
Includes protection circuit to prevent damage to the
parallel port when a connected printer is powered up
or is operated at a higher voltage
(Continued)
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
SuperI OTM is a trademark of National Semiconductor Corporation
IBM MicroChannel PC-AT and PS 2 are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation TL C 11930
TL C 11930 – 1
RRD-B30M65 Printed in U S A
1 page  
FIGURE 2-1
FIGURE 2-2
FIGURE 3-1
FIGURE 4-1
FIGURE 4-2
FIGURE 5-1
FIGURE 5-2
FIGURE 5-3
FIGURE 6-1
FIGURE 6-2
FIGURE 7-1
FIGURE 7-2
FIGURE 7-3
FIGURE 7-4
FIGURE 7-5
FIGURE 7-6
FIGURE 7-7
FIGURE 8-1
FIGURE 9-1
FIGURE 9-2
FIGURE 9-3
FIGURE 9-4
FIGURE 9-5
FIGURE 9-6a
FIGURE 9-6b
FIGURE 9-6c
FIGURE 9-6d
FIGURE 9-7
FIGURE 9-8
FIGURE 9-9
FIGURE 9-10
FIGURE 9-11
FIGURE 9-12
FIGURE 9-13
FIGURE 9-14
FIGURE 9-15
FIGURE 9-16
FIGURE 9-17
FIGURE 9-18
FIGURE 9-19
List of Figures
PC87332VLJ PC87332VLJ-5 Configuration Registers
PC87332 Four Floppy Drive Circuit Example
FDC Functional Block Diagram
FDC Command Structure
IBM Perpendicular and ISO Formats Supported by the Format Command
PC87332 Dynamic Window Margin Performance
Read Data Algorithm State Diagram
Perpendicular Recording Drive R W Head and Pre-Erase Head
PC87332 Composite Serial Data
Reciever FIFO Trigger Level
EPP 1 7 Address Write
EPP 1 7 Address Read
EPP Write with ZWS
EPP 1 9 Address Write
EPP 1 9 Address Read
ECP (Forward) Write Cycle
ECP (Backward) Read Cycle
IDE Interface Signal Equations (Non-DMA)
Clock Timing
Microprocessor Read Timing
Microprocessor Write Timing
Baud Out Timing
Transmitter Timing
Sample Clock Timing
Receiver Timing
Mode Receiver Timing
Timeout Receiver Timing
MODEM Control Timing
DMA Timing
Reset Timing
Write Data Timing
Drive Control Timing
Read Data Timing
IDE Timing
Compatible Mode Parallel Port Interrupt Timing
Extended Mode Parallel Port Interrupt Timing
Typical Parallel Port Data Exchange
Enhanced Parallel Port Timing
ECP Parallel Port Forward Timing Diagram
ECP Parallel Port Backward Timing Diagram
5
5 Page 
1 0 Pin Description (Continued)
Symbol Pin I O
Function
DSKCHG
Normal
Mode
32
I Disk Change This input indicates if the drive door has been opened The state of this pin is available
from the Digital Input register This pin can also be configured as the Read Gate (RGATE) data
separator diagnostic input via the Mode command (see Section 4 2 6)
DSKCHG
PPM
Mode
89
I Disk Change This pin provides an additional Disk Change signal in PPM Mode when PNF e 0 (See
PD4 and Table 7-5 for further information )
DSR1 2 76 68 I Data Set Ready When low this signal indicates that the data set or MODEM is ready to establish a
communications link The DSR signal is a MODEM status input whose condition the CPU can test by
reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel Bit 5 is the
complement of the DSR signal Bit 1 (DDSR) of the MSR indicates whether the DSR input has changed
states since the previous reading of the MSR (See IRRX for further information )
Note Whenever the DDSR bit of the MSR is set an interrupt is generated If MODEM Status interrupts are enabled
DSTRB
78 O Data Strobe This signal is used in EPP mode as a data strobe It is active low (See AFD and Table 7-5
for further information )
DTR1 2
71 63 O Data Terminal Ready When low this output indicates to the MODEM or data set that the UART is
ready to establish a communications link The DTR signal can be set to an active low by programming
bit 0 (DTR) of the MODEM Control Register to a high level A Master Reset operation sets this signal to
its inactive (high) state Loop mode operation holds this signal to its inactive state (See CFG4 – 0 for
further information )
ERR
79 I Error A connected printer sets this input low when it has detected an error This pin has a nominal 25
kX pull-up resistor attached to it (See HDSEL and Table 7-5 for further information )
FDACK
5 I DMA Acknowledge Active low input to acknowledge the FDC DMA request and enable the RD and
WR inputs during a DMA transfer When in PC-AT or Model 30 mode this signal is enabled by bit D3
of the Digital Output Register (DOR) When in PS 2 mode FDACK is always enabled and bit D3 of the
DOR is reserved FDACK should be held high during I O accesses
FDRQ
4 O DMA Request Active high output to signal the DMA controller that a FDC data transfer is needed
When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS 2 mode
FDRQ is always enabled and bit D3 of the DOR is reserved
HCS0
58 O Hard Drive Chip Select 0 This output is active in the AT mode when 1) the hard drive registers from
1F0–1F7h are selected and the primary address is used or 2) the hard drive registers from 170 – 177h
are selected and the secondary address is used This output is inactive if the IDE interface is disabled
via the Configuration Register (See BADDR1 for further information )
HCS1
57 O Hard Drive Chip Select 1 This output is active in the AT mode when 1) the hard drive registers from
3F6–7 are selected and the primary address is used or 2) the hard drive registers from 376 – 377 are
selected and the secondary address is used This output is also inactive if the IDE interface is disabled
via the Configuration Register (See CLK48 for further information )
HDSEL
Normal
Mode
34
O Head Select This output determines which side of the FDD is accessed When active the head
selects side 1 When inactive the head selects side 0
HDSEL
PPM
Mode
79 O Head Select This pin provides an additional Head Select signal in PPM Mode when PNF e 0 (See
ERR and Table 7-5 for further information )
IDED7
60 I O IDE Bit 7 This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the
address range 1F0–1F7h 170 – 177h 3F6h and 376h This pin is in TRI-STATE during read or write
accesses to 3F7h and 377h
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PC87332.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PC87332 | PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller/ Dual UARTs/ IEEE1284 Parallel Port/ and IDE Interfac | National Semiconductor |
| PC87332VLJ | PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller/ Dual UARTs/ IEEE1284 Parallel Port/ and IDE Interfac | National Semiconductor |
| PC87332VLJ-5 | PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller/ Dual UARTs/ IEEE1284 Parallel Port/ and IDE Interfac | National Semiconductor |
| PC87334VJG | SuperI/O 3.3V/5V Floppy Disk Controller/ Dual UARTs/ Infrared/ IEEE1284 Parallel Port/ and IDE Interface | National Semiconductor |
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