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EP1K50FC256 Schematic ( PDF Datasheet ) - Altera

Teilenummer EP1K50FC256
Beschreibung Programmable Logic Device Family
Hersteller Altera
Logo Altera Logo 




Gesamt 30 Seiten
EP1K50FC256 Datasheet, Funktion
June 2001, ver. 3.1
ACEX 1K
Programmable Logic Device Family
®
Data Sheet
Features...
s Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
– Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array
block (EAB)
– Logic array for general logic functions
s High density
– 10,000 to 100,000 typical gates (see Table 1)
– Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
s Cost-efficient programmable architecture for high-volume
applications
– Cost-optimized process
– Low cost solution for high-performance communications
applications
s System-level features
– MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
– Low power consumption
– Bidirectional I/O performance (setup time [tSU] and clock-to-
output delay [tCO]) up to 250 MHz
– Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Table 1. ACEXTM 1K Device Features
Feature
Typical gates
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
EP1K10
10,000
56,000
576
3
12,288
136
EP1K30
30,000
119,000
1,728
6
24,576
171
EP1K50
50,000
199,000
2,880
10
40,960
249
EP1K100
100,000
257,000
4,992
12
49,152
333
Altera Corporation
A-DS-ACEX-3.1
1






EP1K50FC256 Datasheet, Funktion
ACEX 1K Programmable Logic Device Family Data Sheet
f For more information on the configuration of ACEX 1K devices, see the
following documents:
I Configuration Devices for ACEX, APEX, FLEX, & Mercury Devices Data
Sheet
I MasterBlaster Serial/USB Communications Cable Data Sheet
I ByteBlasterMV Parallel Port Download Cable Data Sheet
I BitBlaster Serial Download Cable Data Sheet
ACEX 1K devices are supported by Altera development systems, which
are integrated packages that offer schematic, text (including AHDL), and
waveform design entry, compilation and logic synthesis, full simulation
and worst-case timing analysis, and device configuration. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX workstation-based EDA tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specific features such as carry chains, which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Altera development system includes DesignWare
functions that are optimized for the ACEX 1K device architecture.
The Altera development systems run on Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations.
f
For more information, see the MAX+PLUS II Programmable Logic
Development System & Software Data Sheet and the Quartus Programmable
Logic Development System & Software Data Sheet.
Functional
Description
Each ACEX 1K device contains an enhanced embedded array that
implements memory and specialized logic functions, and a logic array
that implements general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
6 Altera Corporation

6 Page









EP1K50FC256 pdf, datenblatt
ACEX 1K Programmable Logic Device Family Data Sheet
EABs can be used to implement synchronous RAM, which is easier to use
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable signal, while ensuring that its data and
address signals meet setup and hold time specifications relative to the
write enable signal. In contrast, the EAB’s synchronous RAM generates its
own write enable signal and is self-timed with respect to the input or write
clock. A circuit using the EAB’s self-timed RAM must only meet the setup
and hold time specifications of the global clock.
When used as RAM, each EAB can be configured in any of the following
sizes: 256 × 16; 512 × 8; 1,024 × 4; or 2,048 × 2. Figure 5 shows the ACEX 1K
EAB memory configurations.
Figure 5. ACEX 1K EAB Memory Configurations
256 × 16
512 × 8
1,024 × 4
2,048 × 2
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256 × 16 RAM blocks can be combined to form a 256 × 32
block, and two 512 × 8 RAM blocks can be combined to form a
512 × 16 block. Figure 6 shows examples of multiple EAB combination.
Figure 6. Examples of Combining ACEX 1K EABs
256 × 32
256 × 16
512 × 16
512 × 8
256 × 16
512 × 8
12 Altera Corporation

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