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PC87311A Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer PC87311A
Beschreibung Floppy Disk Controller
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
PC87311A Datasheet, Funktion
October 1993
PC87311A PC87312 (SuperI OTM II III)
Floppy Disk Controller with Dual UARTs
Parallel Port and IDE Interface
General Description
The PC87311A 12 incorporates a floppy disk controller
(FDC) two full function UARTs a bidirectional parallel port
and IDE interface control logic in one chip The PC87311A
includes standard AT XT address decoding for on-chip
functions and a Configuration Register offering a single
chip solution to the most commonly used IBM PC
PC-XT and PC-AT peripherals The PC87312 includes
standard AT address decoding for on-chip functions and a
Configuration Register set offering a single chip solution to
the most commonly used ISA EISA and Micro Channel pe-
ripherals
The on-chip FDC is software compatible to the PC8477
which contains a superset of the DP8473 and NEC mPD765
and the N82077 floppy disk controller functions The on-
chip analog data separator requires no external compo-
nents and supports the 4 Mb drive format as well as the
other standard floppy drives used with 5 25 and 3 5 me-
dia
In the PC87311A the UARTs are equivalent to two
INS8250N-Bs or NS16450s The bidirectional parallel port
maintains complete compatibility with the IBM PC XT and
AT In the PC87312 the UARTs are equivalent to two
NS16450s or PC16550s The bidirectional parallel port
maintains complete compatibility with the ISA EISA and Mi-
cro Channel parallel ports
The IDE control logic provides a complete IDE interface ex-
cept for the signal buffers The Configuration Registers con-
sist of three byte-wide registers An Index and a Data Regis-
ter which can be relocated within the ISA I O address space
access the Configuration Registers
Features
Y 100% compatible with IBM PC XT and AT architec-
tures (PC87311A) or ISA EISA and Micro Channel ar-
chitectures (PC87312)
Y FDC
Software compatible with the DP8473 the 765A and
the N82077
16-byte FIFO (default disabled)
Burst and Non-Burst modes
Perpendicular Recording drive support
High performance internal analog data separator (no
external filter components required)
Low power CMOS with power down mode
Y UARTs
Software compatible with the INS8250N-B and the
NS16450 (PC87311A) or PC16550A and PC16450
(PC87312)
Y Parallel Port
Bidirectional under either software or hardware
control
Compatible with all IBM PC XT and AT architectures
(PC87311A) or all ISA EISA and Micro Channel ar-
chitectures (PC87312)
Back Voltage protection circuit against damage
caused when printer is powered up
Y IDE Control Logic
Provides a complete IDE interface except for option-
al buffers
Y Address Decoder
Provides selection of all primary and secondary ISA
addresses including COM 1 – 4
Y 100-pin PQFP package
The PC87311A and PC87312 are pin compatible
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
SuperI OTM is a trademark of National Semiconductor Corporation
IBM PC PC-AT PC-XT and PS 2 are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation TL F 11362
TL F 11362 – 1
RRD-B30M75 Printed in U S A






PC87311A Datasheet, Funktion
1 0 Pin Description
Connection Diagram
Plastic Quad Flatpak EIAJ
Note XTSEL PC87311A only
Order Number PC87311AVF or PC87312VF
See NS Package Number VLJ100A
TL F 11362 – 3
6

6 Page









PC87311A pdf, datenblatt
2 0 Configuration Registers
2 1 OVERVIEW
Three registers constitute the Base Configuration Register
set which controls the set-up of the PC87311A 12 In gen-
eral these registers control the enabling of each major
function (e g FDC UARTs parallel port etc ) the I O ad-
dresses of those functions and whether those functions
power down via hardware control or not These three con-
figuration registers are called the Function Enable Register
(FER) the Function Address (FAR) Register and the Power
and Test Register (PTR)
These registers can be accessed via hardware or software
During reset the PC87311A 12 loads a set of default val-
ues selected by a hardware strapping option into the Config-
uration Registers This defines the setting of all Configura-
tion Registers via hardware
An index and data register pair are used to read and write
these registers Each Configuration Register is pointed to by
the value loaded into the Index Register The data to be
written into the Configuration Register is transferred via the
Data register Reading a Configuration Register is done in a
similar way (i e by pointing to it via the Index Register and
then reading its contents via the Data Register)
Accessing the Configuration Registers in this way requires
only two system I O addresses Since that I O space is
shared by other devices the Index and Data Registers could
still be inadvertantly accessed even though there are only
two registers in this I O address space In order to reduce
the chances of an inadvertant access a simple procedure
(Section 2 2) has been developed
2 2 SOFTWARE CONFIGURATION
If the system requires access to the Configuration Registers
after reset then the following procedure is used to change
data in the registers
1 Determine the default location of the PC87311A 12 In-
dex Register
A Check the two possible default locations (see Table
2-2) by reading them twice The first byte is the ID byte
(88H) The second byte read is always 00H Compare
the data read with the ID byte and then 00h A match
will occur at the correct location Note that the ID byte
is only issued from the Index Register during the first
read after a reset Subsequent reads return the value
loaded into the Index Register Bits 2–6 are reserved
and always read 0
2 Load the Configuration Registers
A Disable CPU interrupts
B Write the index of the Configuration Register (00h–
02h) to the Index Register one time
C Write the correct data for the Configuration Register in
two consecutive write accesses to the Data Register
D Enable CPU interrupts
3 Load the Configuration Registers (read-modify-write)
A Disable CPU interrupts
B Write the index of the Configuration Register (00h–
02h) to the Index Register one time
C Read the configuration data in that register via the
Data Register
D Modify the configuration data
E Write the changed data for the Configuration Register
in two consecutive writes to the Data Register The
register updates on the second consecutive write
F Enable CPU interrupts
A single read access to the Index and Data Registers can
be done at any time without disabling CPU interrupts When
the Index Register is read the last value loaded into the
Index Register will be returned When the Data Register is
read the Configuration Register data pointed to by the In-
dex Register will be returned
TL F 11362 – 38
TL F 11362 – 39
TL F 11362 – 40
FIGURE 2-1 PC87311A 12 Configuration Registers
2 3 HARDWARE CONFIGURATION
During reset 1 of 32 possible sets of default values are
loaded into the Configuration Registers A strapping option
on five pins (CFG0 – 4) selects the set of values that is load-
ed This allows for automatic configuration without software
intervention Table 2-1 shows the 32 possible default con-
figurations The default configuration can be modified by
software at any time after reset by using the access proce-
dure described in the Software Configuration Section
12

12 Page





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